Change in coreboot[master]: soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating

[Subrata Banik (Code Review)]

Attention is currently required from: Paul Menzel, Tim Wawrzynczak, Sridhar Siricilla, Kane Chen.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63293 )

Change subject: soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating
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Patch Set 3:

(1 comment)

Patchset:

PS2:
> @subrata, as per Intel doc#723158, when extern VR is used, then reported issue may not occur. So, I expect developer should enable the UPD if USB2 phy power gating  to be disabled.

I'm concerned about https://b.corp.google.com/issues/221461379#comment4

Do you have power data with and without USB2 PHY being power gated ? if it's <10mW I would like keep this default disable. Do we have conclusive data saying 100% proven that if external VR is used in power delivery, we don't see this issue.