[XS] Change in coreboot[main]: cpu/intel/socket_BGA956: Double DCACHE_RAM_SIZE to 64 kB

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71905?usp=email )

Change subject: cpu/intel/socket_BGA956: Double DCACHE_RAM_SIZE to 64 kB
......................................................................

cpu/intel/socket_BGA956: Double DCACHE_RAM_SIZE to 64 kB

This fixes building lenovo/x200 with VBOOT.
All supported CPUs have enough L2 cache to support this.

Change-Id: Ifd6a16ce36c86349955cd7b7ddb3f74a19c17c4d
Signed-off-by: Arthur Heymans 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71905
Tested-by: build bot (Jenkins) 
Reviewed-by: Martin L Roth 
Reviewed-by: Kyösti Mälkki 
---
M src/cpu/intel/socket_BGA956/Kconfig
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Kyösti Mälkki: Looks good to me, approved
  build bot (Jenkins): Verified
  Martin L Roth: Looks good to me, approved

diff --git a/src/cpu/intel/socket_BGA956/Kconfig b/src/cpu/intel/socket_BGA956/Kconfig
index b56fb88..7c42722 100644
--- a/src/cpu/intel/socket_BGA956/Kconfig
+++ b/src/cpu/intel/socket_BGA956/Kconfig
@@ -10,7 +10,7 @@

config DCACHE_RAM_SIZE
    hex
-	default 0x8000
+	default 0x10000

config DCACHE_BSP_STACK_SIZE
    hex