Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33455
Change subject: ec/google/wilco: Read back from EC RAM after S0ix entry ......................................................................
ec/google/wilco: Read back from EC RAM after S0ix entry
We are seeing an EC interrupt after setting the EC RAM offset that indicates that the EC should transition to S0ix mode and this is preventing the kernel from going into S0ix on the first try.
As a workaround if we read back from the EC RAM while still in the _DSM handler it seems to prevent this problem.
BUG=b:130644677 BRANCH=sarien TEST=ensure s0ix entry works on the first try with sarien
Change-Id: Id607c4c2b14b79d0cd1bcea0c2032be2f2c0c141 Signed-off-by: Duncan Laurie dlaurie@google.com --- M src/ec/google/wilco/acpi/ec.asl 1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/33455/1
diff --git a/src/ec/google/wilco/acpi/ec.asl b/src/ec/google/wilco/acpi/ec.asl index 4fa887b..532f421 100644 --- a/src/ec/google/wilco/acpi/ec.asl +++ b/src/ec/google/wilco/acpi/ec.asl @@ -154,6 +154,12 @@ If (Arg0) { Printf ("EC Enter S0ix") W (CSEX, One) + + /* + * Read back from EC RAM after enabling S0ix + * to prevent EC from aborting S0ix entry. + */ + R (EVT1) } Else { Printf ("EC Exit S0ix") W (CSEX, Zero)
Shaunak Saha has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33455 )
Change subject: ec/google/wilco: Read back from EC RAM after S0ix entry ......................................................................
Patch Set 1: Code-Review+1
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33455 )
Change subject: ec/google/wilco: Read back from EC RAM after S0ix entry ......................................................................
Patch Set 1: Code-Review+2
Duncan Laurie has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/33455 )
Change subject: ec/google/wilco: Read back from EC RAM after S0ix entry ......................................................................
ec/google/wilco: Read back from EC RAM after S0ix entry
We are seeing an EC interrupt after setting the EC RAM offset that indicates that the EC should transition to S0ix mode and this is preventing the kernel from going into S0ix on the first try.
As a workaround if we read back from the EC RAM while still in the _DSM handler it seems to prevent this problem.
BUG=b:130644677 BRANCH=sarien TEST=ensure s0ix entry works on the first try with sarien
Change-Id: Id607c4c2b14b79d0cd1bcea0c2032be2f2c0c141 Signed-off-by: Duncan Laurie dlaurie@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/33455 Reviewed-by: Shaunak Saha shaunak.saha@intel.corp-partner.google.com Reviewed-by: Furquan Shaikh furquan@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/ec/google/wilco/acpi/ec.asl 1 file changed, 6 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Shaunak Saha: Looks good to me, but someone else must approve
diff --git a/src/ec/google/wilco/acpi/ec.asl b/src/ec/google/wilco/acpi/ec.asl index 4fa887b..532f421 100644 --- a/src/ec/google/wilco/acpi/ec.asl +++ b/src/ec/google/wilco/acpi/ec.asl @@ -154,6 +154,12 @@ If (Arg0) { Printf ("EC Enter S0ix") W (CSEX, One) + + /* + * Read back from EC RAM after enabling S0ix + * to prevent EC from aborting S0ix entry. + */ + R (EVT1) } Else { Printf ("EC Exit S0ix") W (CSEX, Zero)
-
Duncan Laurie (Code Review) -
Furquan Shaikh (Code Review)
-
Shaunak Saha (Code Review)