Attention is currently required from: Felix Singer, Nico Huber, Subrata Banik, Maxim Polyakov, Tim Wawrzynczak, Angel Pons, Nick Vaccaro. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62138 )
Change subject: apollolake mainboards: Set PMC as hidden in devicetree ......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
uhm, sorry for causing confusion. looks like I am confused by apl/glk fsp being more confusing than other platforms o.
yes, looks like PMC disabling been handled by FSP-S main API for all other SOC.
O That cold reset seems to be caused by disabling PMC pci functions
yes.
(PWM, ISH, SATA,...., P0, P1, P2,... - what is P0-P3? o.O) so the log entry could be caused by any of them
Sorry, I'm unable to follow this one.
Well, there's not just `the PMC function` but that message is being caused by disabling any of the PMC-related functions PWM, ISH, SATA, etc. Take a look at `GeminilakeSiliconPkg/SouthCluster/Library/Private/PeiScInitLib/ScInit.c` or grep for 'SC_PMC_FUNCTION_DISABLE_COLD_RESET' on the source. What I want so say: that message doesn't tell us, when the PMC main function is disabled.
Anyway, I had another look at the code and found it: `B_SC_PCH_PCR_PSFX_T0_SHDW_CFG_DIS_CFGDIS` is being set in the PSF3 register `R_SC_PCH_PCR_PSF3_T0_SHDW_PMC_PMC_REG_BASE` in `ConfigurePmcAtBoot()` which is called at EndOfFirmware notify.
So yes, the pci cfg space is present during PCI enumeration on APL/GLK. On other platforms that's not the case AFAICS.
-
Michael Niewöhner (Code Review)