Change in coreboot[master]: src/soc/intel/common: Configure the chip select state correctly

[Aamir Bohra (Code Review)]

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/27889

Change subject: src/soc/intel/common: Configure the chip select state correctly
......................................................................

src/soc/intel/common: Configure the chip select state correctly

This implementation updates the chip select control register
programming in gspi controller setup call to program the correct
bit fields for chip select state.

Change-Id: Ifab37b0003f09a680024d5b155ab0bb157920a53
Signed-off-by: Aamir Bohra 
---
M src/soc/intel/common/block/gspi/gspi.c
1 file changed, 1 insertion(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/27889/1

diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c
index 35c34ce..fc7dd46 100644
--- a/src/soc/intel/common/block/gspi/gspi.c
+++ b/src/soc/intel/common/block/gspi/gspi.c
@@ -481,12 +481,9 @@
    cs_ctrl = CS_MODE_SW | CS_0;
    pol = gspi_csctrl_polarity(cfg.cs_polarity);
    cs_ctrl |= pol << CS_0_POL_SHIFT;
-	cs_ctrl |= gspi_csctrl_state(pol, CS_DEASSERT);
+	cs_ctrl |= gspi_csctrl_state(pol, CS_DEASSERT) << CS_STATE_SHIFT;
    gspi_write_mmio_reg(p, SPI_CS_CONTROL, cs_ctrl);

-	/* De-assert chip select. */
-	__gspi_cs_change(p, CS_DEASSERT);
-
    /* Disable SPI controller. */
    gspi_write_mmio_reg(p, SSCR0, SSCR0_SSE_DISABLE);