[S] Change in coreboot[master]: soc/qualcomm: Update the wait time for checking PCIe link up

[Shelley Chen (Code Review)]

Shelley Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/67884 )

Change subject: soc/qualcomm: Update the wait time for checking PCIe link up
......................................................................

soc/qualcomm: Update the wait time for checking PCIe link up

Currently, after the PCIe link is initialized, we wait 100ms every
time the link is not up anymore.  However, this causes significant
delay.  Assuming the first check is false, we'd like to increase the
frequency of checks for the link to be up.  Changing to check every
10ms instead.  This seems to save about 90ms in the device
configuration stage of bootup on herobrine.

BUG=b:218406702
BRANCH=None
TEST=reboot from AP console (on herobrine)
     prior to fix (from cbmem dump):
         40:device configuration 919,391 (202,861)
     after fix (from cbmem dump):
         40:device configuration 826,294 (112,729)

Change-Id: Ic67e7207c1e9f589b34705dc24f5d1ea423e2d56
Signed-off-by: Shelley Chen 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67884
Tested-by: build bot (Jenkins) 
Reviewed-by: Tim Wawrzynczak 
Reviewed-by: mturney mturney 
Reviewed-by: Douglas Anderson 
---
M src/soc/qualcomm/common/include/soc/pcie.h
1 file changed, 32 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Douglas Anderson: Looks good to me, approved
  Tim Wawrzynczak: Looks good to me, but someone else must approve
  mturney mturney: Looks good to me, but someone else must approve

diff --git a/src/soc/qualcomm/common/include/soc/pcie.h b/src/soc/qualcomm/common/include/soc/pcie.h
index 09ea671..5aa315c 100644
--- a/src/soc/qualcomm/common/include/soc/pcie.h
+++ b/src/soc/qualcomm/common/include/soc/pcie.h
@@ -48,8 +48,8 @@
 #define LINK_SPEED_GEN_1		0x1
 #define LINK_SPEED_GEN_2		0x2
 #define LINK_SPEED_GEN_3		0x3
-#define PCIE_LINK_UP_MS			100
-#define LINK_WAIT_MAX_RETRIES		10
+#define PCIE_LINK_UP_MS			10
+#define LINK_WAIT_MAX_RETRIES		100

#define COMMAND_MASK			0xffff