Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39115 )
Change subject: mb/google/dedede: Add WLAN configuration ......................................................................
mb/google/dedede: Add WLAN configuration
Turn on CNVi device. Turn on PCIe Root port that hosts WLAN device. Configure PCIe Clk Source and Clk Request mapping. Configure GPIOs used for WLAN.
BUG=None TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com Change-Id: I9bb8e57cdb688bc544929c94af380b9ef1d936a2 --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/baseboard/gpio.c M src/mainboard/google/dedede/variants/waddledoo/overridetree.cb 3 files changed, 34 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/39115/1
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index ea7689e..f27251d 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -70,6 +70,14 @@ [PchSerialIoIndexUART2] = PchSerialIoSkipInit, }"
+ # PCIe root port 4 hosts M.2 E-key WLAN and uses Clk Source 4. The concerned + # Clk Source maps to Clk Request 4. Note the indices are off by 1 for + # zero-indexing. + register "PcieRpEnable[3]" = "1" + register "PcieClkSrcUsage[3]" = "3" + register "PcieClkSrcClkReq[3]" = "3" + + # Enable EMMC HS400 mode register "ScsEmmcHs400Enabled" = "1"
@@ -119,7 +127,10 @@ device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 off end # PMC SRAM - device pci 14.3 off end # CNVi wifi + chip drivers/intel/wifi + register "wake" = "GPE0_PME_B0" + device pci 14.3 on end # CNVi wifi + end device pci 14.5 off end # SDCard device pci 15.0 on end # I2C 0 device pci 15.1 on end # I2C 1 @@ -137,7 +148,7 @@ device pci 1c.0 off end # PCI Express Root Port 1 device pci 1c.1 off end # PCI Express Root Port 2 device pci 1c.2 off end # PCI Express Root Port 3 - device pci 1c.3 off end # PCI Express Root Port 4 - WLAN + device pci 1c.3 on end # PCI Express Root Port 4 - WLAN device pci 1c.4 off end # PCI Express Root Port 5 device pci 1c.5 off end # PCI Express Root Port 6 device pci 1c.6 off end # PCI Express Root Port 7 diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index 0e2a168..dc90e60 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -64,8 +64,8 @@ PAD_NC(GPP_B6, NONE), /* B7 : PCIE_CLKREQ2_N */ PAD_NC(GPP_B7, NONE), - /* B8 : PCIE_CLKREQ3_N */ - PAD_NC(GPP_B8, NONE), + /* B8 : WLAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* B9 : PCIE_CLKREQ4_N */ PAD_NC(GPP_B9, NONE), /* B10 : PCIE_CLKREQ5_N */ @@ -149,11 +149,11 @@ /* D0 : WWAN_HOST_WAKE */ PAD_NC(GPP_D0, NONE), /* D1 : WLAN_PERST_L */ - PAD_NC(GPP_D1, NONE), + PAD_CFG_GPO(GPP_D1, 1, DEEP), /* D2 : WLAN_INT_L */ - PAD_NC(GPP_D2, NONE), + PAD_CFG_GPI_SCI_LOW(GPP_D2, NONE, DEEP, EDGE_SINGLE), /* D3 : WLAN_PCIE_WAKE_ODL */ - PAD_NC(GPP_D3, NONE), + PAD_CFG_GPI(GPP_D3, NONE, DEEP), /* D4 : TOUCH_INT_ODL */ PAD_NC(GPP_D4, NONE), /* D5 : TOUCH_RESET_L */ @@ -185,11 +185,11 @@ /* D18 : I2S_MCLK */ PAD_NC(GPP_D18, NONE), /* D19 : WWAN_WLAN_COEX1 */ - PAD_NC(GPP_D19, NONE), + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF2), /* D20 : WWAN_WLAN_COEX2 */ - PAD_NC(GPP_D20, NONE), + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF2), /* D21 : WWAN_WLAN_COEX3 */ - PAD_NC(GPP_D21, NONE), + PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), /* D22 : AP_I2C_SUB_SDA*/ PAD_NC(GPP_D22, NONE), /* D23 : AP_I2C_SUB_SCL */ @@ -325,7 +325,7 @@ /* H17 : WWAN_RST_L */ PAD_NC(GPP_H17, NONE), /* H18 : WLAN_DISABLE_L */ - PAD_NC(GPP_H18, NONE), + PAD_CFG_GPO(GPP_H18, 1, DEEP), /* H19 : BT_DISABLE_L */ PAD_NC(GPP_H19, NONE),
@@ -380,7 +380,7 @@ /* GPD7 : GPP_GPD7 */ PAD_NC(GPD7, NONE), /* GPD8 : WLAN_SUSCLK */ - PAD_NC(GPD8, NONE), + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* GPD9 : AP_SLP_WLAN_L */ PAD_NC(GPD9, NONE), /* GPD10 : AP_SPL_S5_L */ @@ -399,6 +399,9 @@ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + + /* D1 : WLAN_PERST_L */ + PAD_CFG_GPO(GPP_D1, 1, DEEP), };
const struct pad_config *__weak variant_gpio_table(size_t *num) diff --git a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb index ac9d576..f0bdb63 100644 --- a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb @@ -1,3 +1,10 @@ chip soc/intel/tigerlake - device domain 0 on end + device domain 0 on + device pci 1c.3 on + chip drivers/intel/wifi + register "wake" = "GPE0_DW2_03" + device pci 00.0 on end + end + end # PCI Express Root Port 4 - WLAN + end end
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39115 )
Change subject: mb/google/dedede: Add WLAN configuration ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39115/2/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39115/2/src/mainboard/google/dedede... PS2, Line 384: AP_SLP_WLAN_L Should this be configured in this commit too?
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39115 )
Change subject: mb/google/dedede: Add WLAN configuration ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39115/2/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/39115/2/src/mainboard/google/dedede... PS2, Line 76: register "PcieRpEnable[3]" = "1" This has to be PcieRpEnable[8] instead. The internal and external PCIe mapping are documented in Chapter 14 PCI Express* Port / Controller Mapping section EDS vol1
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39115 )
Change subject: mb/google/dedede: Add WLAN configuration ......................................................................
Patch Set 2:
(3 comments)
https://review.coreboot.org/c/coreboot/+/39115/2/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39115/2/src/mainboard/google/dedede... PS2, Line 15: gpio_table Cnvi would need below GPIO also:
/* MODEM CLKREQ */ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3),
/* Cnvi RST */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
https://review.coreboot.org/c/coreboot/+/39115/2/src/mainboard/google/dedede... PS2, Line 330: PAD_NC(GPP_H19, NONE), BT disable needs to driven high as well
https://review.coreboot.org/c/coreboot/+/39115/2/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/waddledoo/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/39115/2/src/mainboard/google/dedede... PS2, Line 3: 3 1c.7
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39115 )
Change subject: mb/google/dedede: Add WLAN configuration ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39115/2/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/39115/2/src/mainboard/google/dedede... PS2, Line 76: register "PcieRpEnable[3]" = "1"
This has to be PcieRpEnable[8] instead. […]
sorry *register "PcieRpEnable[7]" = "1"
https://review.coreboot.org/c/coreboot/+/39115/2/src/mainboard/google/dedede... PS2, Line 76: register "PcieRpEnable[3]" = "1" : register "PcieClkSrcUsage[3]" = "3" : register "PcieClkSrcClkReq[3]" = "3" Will have to set PcieRpEnable[x] =0 for Pcie port not used and clock src usage to 0xff not used. Can we cover it in this CL?
Hello Aamir Bohra, Tim Wawrzynczak, Justin TerAvest, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39115
to look at the new patch set (#3).
Change subject: mb/google/dedede: Add WLAN configuration ......................................................................
mb/google/dedede: Add WLAN configuration
Turn on CNVi device. Turn on PCIe Root port that hosts WLAN device. Configure PCIe Clk Source and Clk Request mapping. Configure GPIOs used for WLAN - both CNVi and M.2.
BUG=None TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com Change-Id: I9bb8e57cdb688bc544929c94af380b9ef1d936a2 --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/baseboard/gpio.c M src/mainboard/google/dedede/variants/waddledoo/overridetree.cb 3 files changed, 42 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/39115/3
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39115 )
Change subject: mb/google/dedede: Add WLAN configuration ......................................................................
Patch Set 3:
(6 comments)
https://review.coreboot.org/c/coreboot/+/39115/2/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/39115/2/src/mainboard/google/dedede... PS2, Line 76: register "PcieRpEnable[3]" = "1"
sorry *register "PcieRpEnable[7]" = "1"
Done
https://review.coreboot.org/c/coreboot/+/39115/2/src/mainboard/google/dedede... PS2, Line 76: register "PcieRpEnable[3]" = "1" : register "PcieClkSrcUsage[3]" = "3" : register "PcieClkSrcClkReq[3]" = "3"
Will have to set PcieRpEnable[x] =0 for Pcie port not used and clock src usage to 0xff not used. […]
Done
https://review.coreboot.org/c/coreboot/+/39115/2/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39115/2/src/mainboard/google/dedede... PS2, Line 15: gpio_table
Cnvi would need below GPIO also: […]
Done
https://review.coreboot.org/c/coreboot/+/39115/2/src/mainboard/google/dedede... PS2, Line 330: PAD_NC(GPP_H19, NONE),
BT disable needs to driven high as well
Done
https://review.coreboot.org/c/coreboot/+/39115/2/src/mainboard/google/dedede... PS2, Line 384: AP_SLP_WLAN_L
Should this be configured in this commit too?
Done
https://review.coreboot.org/c/coreboot/+/39115/2/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/waddledoo/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/39115/2/src/mainboard/google/dedede... PS2, Line 3: 3
1c. […]
Done
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39115 )
Change subject: mb/google/dedede: Add WLAN configuration ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39115/3/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/39115/3/src/mainboard/google/dedede... PS3, Line 102: register "PcieClkSrcClkReq[3]" = "7" ClkReq-to-ClkSrc mapping for CLK SRC 3 register "PcieClkSrcClkReq[3]" = "0x03"
Varshit B Pandya has uploaded a new patch set (#4) to the change originally created by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/39115 )
Change subject: mb/google/dedede: Add WLAN configuration ......................................................................
mb/google/dedede: Add WLAN configuration
Turn on CNVi device. Turn on PCIe Root port that hosts WLAN device. Configure PCIe Clk Source and Clk Request mapping. Configure GPIOs used for WLAN - both CNVi and M.2.
BUG=None TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com Change-Id: I9bb8e57cdb688bc544929c94af380b9ef1d936a2 --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/baseboard/gpio.c M src/mainboard/google/dedede/variants/waddledoo/overridetree.cb 3 files changed, 41 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/39115/4
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39115 )
Change subject: mb/google/dedede: Add WLAN configuration ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39115/4/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/39115/4/src/mainboard/google/dedede... PS4, Line 94: register "PcieClkSrcUsage[3]" = "7" Is this configuration correct?
Hello Varshit B Pandya, build bot (Jenkins), Furquan Shaikh, Justin TerAvest, Aamir Bohra, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39115
to look at the new patch set (#5).
Change subject: mb/google/dedede: Add WLAN configuration ......................................................................
mb/google/dedede: Add WLAN configuration
Turn on CNVi device. Turn on PCIe Root port that hosts WLAN device. Configure PCIe Clk Source and Clk Request mapping. Configure GPIOs used for WLAN - both CNVi and M.2.
BUG=None TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com Change-Id: I9bb8e57cdb688bc544929c94af380b9ef1d936a2 --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/baseboard/gpio.c M src/mainboard/google/dedede/variants/waddledoo/overridetree.cb 3 files changed, 41 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/39115/5
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39115 )
Change subject: mb/google/dedede: Add WLAN configuration ......................................................................
Patch Set 5: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/39115/4/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/39115/4/src/mainboard/google/dedede... PS4, Line 94: register "PcieClkSrcUsage[3]" = "7"
Is this configuration correct?
Yes, the port8 uses Clk source 3
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39115 )
Change subject: mb/google/dedede: Add WLAN configuration ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39115/3/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/39115/3/src/mainboard/google/dedede... PS3, Line 102: register "PcieClkSrcClkReq[3]" = "7"
ClkReq-to-ClkSrc mapping for CLK SRC 3 […]
Done
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39115 )
Change subject: mb/google/dedede: Add WLAN configuration ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39115/4/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/39115/4/src/mainboard/google/dedede... PS4, Line 94: register "PcieClkSrcUsage[3]" = "7"
Yes, the port8 uses Clk source 3
Done
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39115 )
Change subject: mb/google/dedede: Add WLAN configuration ......................................................................
Patch Set 5:
(6 comments)
https://review.coreboot.org/c/coreboot/+/39115/5/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39115/5/src/mainboard/google/dedede... PS5, Line 154: PAD_CFG_GPI_SCI_LOW What is this line used for?
https://review.coreboot.org/c/coreboot/+/39115/5/src/mainboard/google/dedede... PS5, Line 156: GPP_D3 Isn't this supposed to be the wake? I don't think PAD_CFG_GPI is the right pad configuration.
https://review.coreboot.org/c/coreboot/+/39115/5/src/mainboard/google/dedede... PS5, Line 188: PAD_CFG_NF(GPP_D19, NONE, DEEP, NF2), : /* D20 : WWAN_WLAN_COEX2 */ : PAD_CFG_NF(GPP_D20, NONE, DEEP, NF2), : /* D21 : WWAN_WLAN_COEX3 */ : PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), Are these configured for CNVi or PCIe?
https://review.coreboot.org/c/coreboot/+/39115/5/src/mainboard/google/dedede... PS5, Line 330: GPP_H19 Just a note. This will have to be exposed in ACPI tables to allow kernel driver to reset bluetooth if required. See Hatch or Octopus as examples. It can be handled as a follow-up.
https://review.coreboot.org/c/coreboot/+/39115/5/src/mainboard/google/dedede... PS5, Line 385: PAD_CFG_NF(GPD9, NONE, DEEP, NF1), Is this actually connected in hardware? I don't see it going anywhere.
https://review.coreboot.org/c/coreboot/+/39115/5/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/waddledoo/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/39115/5/src/mainboard/google/dedede... PS5, Line 6: 00.0 Just a note: This device is being set up in the override tree, but its clock source and other PCIe settings are being done in baseboard devicetree?
Hello Varshit B Pandya, build bot (Jenkins), Furquan Shaikh, Justin TerAvest, Aamir Bohra, Aamir Bohra, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39115
to look at the new patch set (#6).
Change subject: mb/google/dedede: Add WLAN configuration ......................................................................
mb/google/dedede: Add WLAN configuration
Turn on CNVi device. Turn on PCIe Root port that hosts WLAN device. Configure PCIe Clk Source and Clk Request mapping. Configure GPIOs used for WLAN - both CNVi and M.2.
BUG=None TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com Change-Id: I9bb8e57cdb688bc544929c94af380b9ef1d936a2 --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/baseboard/gpio.c M src/mainboard/google/dedede/variants/waddledoo/overridetree.cb 3 files changed, 39 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/39115/6
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39115 )
Change subject: mb/google/dedede: Add WLAN configuration ......................................................................
Patch Set 7:
(6 comments)
https://review.coreboot.org/c/coreboot/+/39115/5/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39115/5/src/mainboard/google/dedede... PS5, Line 154: PAD_CFG_GPI_SCI_LOW
What is this line used for?
For PCIe based WLAN to trigger interrupt to AP when AP is in S0 state.
https://review.coreboot.org/c/coreboot/+/39115/5/src/mainboard/google/dedede... PS5, Line 156: GPP_D3
Isn't this supposed to be the wake? I don't think PAD_CFG_GPI is the right pad configuration.
Yes, this is supposed to be wake line. Let me check it.
https://review.coreboot.org/c/coreboot/+/39115/5/src/mainboard/google/dedede... PS5, Line 188: PAD_CFG_NF(GPP_D19, NONE, DEEP, NF2), : /* D20 : WWAN_WLAN_COEX2 */ : PAD_CFG_NF(GPP_D20, NONE, DEEP, NF2), : /* D21 : WWAN_WLAN_COEX3 */ : PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
Are these configured for CNVi or PCIe?
Based on the EDS, GPP_D19/20 are configured for PCIe and GPP_D21 for CNVi. Used the similar one from TGL.
https://review.coreboot.org/c/coreboot/+/39115/5/src/mainboard/google/dedede... PS5, Line 330: GPP_H19
Just a note. […]
True, I have to add a device tree object under XHCI for Bluetooth.
https://review.coreboot.org/c/coreboot/+/39115/5/src/mainboard/google/dedede... PS5, Line 385: PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
Is this actually connected in hardware? I don't see it going anywhere.
You are correct. Is it something that needs to be fixed in HW? Same for SLP_S5_L
https://review.coreboot.org/c/coreboot/+/39115/5/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/waddledoo/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/39115/5/src/mainboard/google/dedede... PS5, Line 6: 00.0
Just a note: This device is being set up in the override tree, but its clock source and other PCIe s […]
True, I am setting it up here because Dee uses a different PCIe WiFi part. Hence added this in the override tree.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39115 )
Change subject: mb/google/dedede: Add WLAN configuration ......................................................................
Patch Set 7:
(3 comments)
https://review.coreboot.org/c/coreboot/+/39115/5/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39115/5/src/mainboard/google/dedede... PS5, Line 154: PAD_CFG_GPI_SCI_LOW
For PCIe based WLAN to trigger interrupt to AP when AP is in S0 state.
Don't you need to configure the line to be routed to APIC in that case? Also, how does the kernel driver get to know about this interrupt line? Is it exposed in ACPI?
https://review.coreboot.org/c/coreboot/+/39115/5/src/mainboard/google/dedede... PS5, Line 188: PAD_CFG_NF(GPP_D19, NONE, DEEP, NF2), : /* D20 : WWAN_WLAN_COEX2 */ : PAD_CFG_NF(GPP_D20, NONE, DEEP, NF2), : /* D21 : WWAN_WLAN_COEX3 */ : PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
Based on the EDS, GPP_D19/20 are configured for PCIe and GPP_D21 for CNVi. […]
Interesting. It would be good to check with Intel on this. I believe we would want all lines to be configured for CNVi when using that.
https://review.coreboot.org/c/coreboot/+/39115/5/src/mainboard/google/dedede... PS5, Line 385: PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
You are correct. […]
No. I don't think we ever use it. This can be just left as PAD_NC
Aamir Bohra has uploaded a new patch set (#8) to the change originally created by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/39115 )
Change subject: mb/google/dedede: Add WLAN configuration ......................................................................
mb/google/dedede: Add WLAN configuration
Turn on CNVi device. Turn on PCIe Root port that hosts WLAN device. Configure PCIe Clk Source and Clk Request mapping. Configure GPIOs used for WLAN - both CNVi and M.2.
BUG=None TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com Change-Id: I9bb8e57cdb688bc544929c94af380b9ef1d936a2 --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/baseboard/gpio.c M src/mainboard/google/dedede/variants/waddledoo/overridetree.cb 3 files changed, 39 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/39115/8
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39115 )
Change subject: mb/google/dedede: Add WLAN configuration ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39115/8/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/39115/8/src/mainboard/google/dedede... PS8, Line 192: device pci 1c.7 on end # PCI Express Root Port 8 - WLAN don't you need chip drivers/intel/wifi register "wake" = "???" # assuming there is a wake signal device pci 00.0 on end end here ?
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39115 )
Change subject: mb/google/dedede: Add WLAN configuration ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39115/8/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/39115/8/src/mainboard/google/dedede... PS8, Line 192: device pci 1c.7 on end # PCI Express Root Port 8 - WLAN
don't you need […]
Yes, it is applied in the override tree because we will be dual-sourcing M.2 Wifi module
Hello Varshit B Pandya, build bot (Jenkins), Furquan Shaikh, Justin TerAvest, Aamir Bohra, Aamir Bohra, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39115
to look at the new patch set (#9).
Change subject: mb/google/dedede: Add WLAN configuration ......................................................................
mb/google/dedede: Add WLAN configuration
Turn on CNVi device. Turn on PCIe Root port that hosts WLAN device. Configure PCIe Clk Source and Clk Request mapping. Configure GPIOs used for WLAN - both CNVi and M.2.
BUG=None TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com Change-Id: I9bb8e57cdb688bc544929c94af380b9ef1d936a2 --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/baseboard/gpio.c M src/mainboard/google/dedede/variants/waddledoo/overridetree.cb 3 files changed, 37 insertions(+), 23 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/39115/9
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39115 )
Change subject: mb/google/dedede: Add WLAN configuration ......................................................................
Patch Set 9:
(5 comments)
https://review.coreboot.org/c/coreboot/+/39115/5/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39115/5/src/mainboard/google/dedede... PS5, Line 156: GPP_D3
Yes, this is supposed to be wake line. Let me check it.
Done
https://review.coreboot.org/c/coreboot/+/39115/5/src/mainboard/google/dedede... PS5, Line 188: PAD_CFG_NF(GPP_D19, NONE, DEEP, NF2), : /* D20 : WWAN_WLAN_COEX2 */ : PAD_CFG_NF(GPP_D20, NONE, DEEP, NF2), : /* D21 : WWAN_WLAN_COEX3 */ : PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
Interesting. It would be good to check with Intel on this. […]
Aamir, Can you or someone from Intel help to address this comment?
https://review.coreboot.org/c/coreboot/+/39115/5/src/mainboard/google/dedede... PS5, Line 330: GPP_H19
True, I have to add a device tree object under XHCI for Bluetooth.
Done here - https://review.coreboot.org/c/coreboot/+/39446
https://review.coreboot.org/c/coreboot/+/39115/5/src/mainboard/google/dedede... PS5, Line 385: PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
No. I don't think we ever use it. […]
Done
https://review.coreboot.org/c/coreboot/+/39115/5/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/waddledoo/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/39115/5/src/mainboard/google/dedede... PS5, Line 6: 00.0
True, I am setting it up here because Dee uses a different PCIe WiFi part. […]
Ack
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39115 )
Change subject: mb/google/dedede: Add WLAN configuration ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39115/9/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39115/9/src/mainboard/google/dedede... PS9, Line 387: AP_SPL_S5_L Fix the typo.
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39115 )
Change subject: mb/google/dedede: Add WLAN configuration ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39115/5/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39115/5/src/mainboard/google/dedede... PS5, Line 188: PAD_CFG_NF(GPP_D19, NONE, DEEP, NF2), : /* D20 : WWAN_WLAN_COEX2 */ : PAD_CFG_NF(GPP_D20, NONE, DEEP, NF2), : /* D21 : WWAN_WLAN_COEX3 */ : PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
Aamir, Can you or someone from Intel help to address this comment?
Hi Karthik, I checked, these have to set to native in case we use integrated WLAN(Cnvi) + WWAN. Also I see from EDS , only NF1 is defined for these pins, can you please check?
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39115 )
Change subject: mb/google/dedede: Add WLAN configuration ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39115/5/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39115/5/src/mainboard/google/dedede... PS5, Line 188: PAD_CFG_NF(GPP_D19, NONE, DEEP, NF2), : /* D20 : WWAN_WLAN_COEX2 */ : PAD_CFG_NF(GPP_D20, NONE, DEEP, NF2), : /* D21 : WWAN_WLAN_COEX3 */ : PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
Hi Karthik, I checked, these have to set to native in case we use integrated WLAN(Cnvi) + WWAN. […]
A follow-up question: How is the co-existence managed in the case of M.2 WLAN + WWAN?
Based on the discussion here, I will leave it as NC so that we can configure it accordingly for the concerned SKUs where WWAN is present.
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39115 )
Change subject: mb/google/dedede: Add WLAN configuration ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39115/5/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39115/5/src/mainboard/google/dedede... PS5, Line 188: PAD_CFG_NF(GPP_D19, NONE, DEEP, NF2), : /* D20 : WWAN_WLAN_COEX2 */ : PAD_CFG_NF(GPP_D20, NONE, DEEP, NF2), : /* D21 : WWAN_WLAN_COEX3 */ : PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
A follow-up question: How is the co-existence managed in the case of M.2 WLAN + WWAN? […]
Looking at the previous platforms, I think it can be kept as NF1 for all the CoEX GPIOs.
Still I have the follow-up question regarding how the CoEX is managed for M.2 WLAN + WWAN.
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39115 )
Change subject: mb/google/dedede: Add WLAN configuration ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39115/5/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39115/5/src/mainboard/google/dedede... PS5, Line 154: PAD_CFG_GPI_SCI_LOW
Don't you need to configure the line to be routed to APIC in that case? Also, how does the kernel dr […]
After further investigation in hatch - eventhough the line is configured to be routed to APIC, there is no ACPI configuration to pass the GPIO info to kernel.
Also even in some of the variants of hatch, it is marked as Not Connected.
Aamir, Do you know how this line is used? If not, I will mark it as PAD_NC.
Hello Varshit B Pandya, build bot (Jenkins), Furquan Shaikh, Justin TerAvest, Aamir Bohra, Aamir Bohra, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39115
to look at the new patch set (#10).
Change subject: mb/google/dedede: Add WLAN configuration ......................................................................
mb/google/dedede: Add WLAN configuration
Turn on CNVi device. Turn on PCIe Root port that hosts WLAN device. Configure PCIe Clk Source and Clk Request mapping. Configure GPIOs used for WLAN - both CNVi and M.2.
BUG=None TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com Change-Id: I9bb8e57cdb688bc544929c94af380b9ef1d936a2 --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/baseboard/gpio.c M src/mainboard/google/dedede/variants/waddledoo/overridetree.cb 3 files changed, 36 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/39115/10
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39115 )
Change subject: mb/google/dedede: Add WLAN configuration ......................................................................
Patch Set 10:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39115/8/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/39115/8/src/mainboard/google/dedede... PS8, Line 192: device pci 1c.7 on end # PCI Express Root Port 8 - WLAN
Yes, it is applied in the override tree because we will be dual-sourcing M. […]
Done
https://review.coreboot.org/c/coreboot/+/39115/9/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39115/9/src/mainboard/google/dedede... PS9, Line 387: AP_SPL_S5_L
Fix the typo.
Done
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39115 )
Change subject: mb/google/dedede: Add WLAN configuration ......................................................................
Patch Set 10:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39115/5/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39115/5/src/mainboard/google/dedede... PS5, Line 154: PAD_CFG_GPI_SCI_LOW
After further investigation in hatch - eventhough the line is configured to be routed to APIC, there […]
I see it routed to I2C_IRQ on WLAN connector, since I2C SCL and SDA on connector is unstuffed, we are not using it, safe to configure as NC.
https://review.coreboot.org/c/coreboot/+/39115/5/src/mainboard/google/dedede... PS5, Line 188: PAD_CFG_NF(GPP_D19, NONE, DEEP, NF2), : /* D20 : WWAN_WLAN_COEX2 */ : PAD_CFG_NF(GPP_D20, NONE, DEEP, NF2), : /* D21 : WWAN_WLAN_COEX3 */ : PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
Looking at the previous platforms, I think it can be kept as NF1 for all the CoEX GPIOs. […]
Still I have the follow-up question regarding how the CoEX is managed for M.2 WLAN + WWAN.
for the discrete case? IIRC(checked with Anil too), these lines have to be routed between the Modules.
Hello Varshit B Pandya, build bot (Jenkins), Furquan Shaikh, Justin TerAvest, Aamir Bohra, Aamir Bohra, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39115
to look at the new patch set (#11).
Change subject: mb/google/dedede: Add WLAN configuration ......................................................................
mb/google/dedede: Add WLAN configuration
Turn on CNVi device. Turn on PCIe Root port that hosts WLAN device. Configure PCIe Clk Source and Clk Request mapping. Configure GPIOs used for WLAN - both CNVi and M.2.
BUG=None TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com Change-Id: I9bb8e57cdb688bc544929c94af380b9ef1d936a2 --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/baseboard/gpio.c M src/mainboard/google/dedede/variants/waddledoo/overridetree.cb 3 files changed, 35 insertions(+), 19 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/39115/11
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39115 )
Change subject: mb/google/dedede: Add WLAN configuration ......................................................................
Patch Set 11:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39115/5/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39115/5/src/mainboard/google/dedede... PS5, Line 154: PAD_CFG_GPI_SCI_LOW
I see it routed to I2C_IRQ on WLAN connector, since I2C SCL and SDA on connector is unstuffed, we ar […]
So if I understand correctly it is a way for WLAN connector to interrupt AP regarding some data is ready to be read over I2C. Is that correct?
Since I2C lines are not stuffed, you are suggesting that the Interrupt line is not required.
https://review.coreboot.org/c/coreboot/+/39115/5/src/mainboard/google/dedede... PS5, Line 188: PAD_CFG_NF(GPP_D19, NONE, DEEP, NF2), : /* D20 : WWAN_WLAN_COEX2 */ : PAD_CFG_NF(GPP_D20, NONE, DEEP, NF2), : /* D21 : WWAN_WLAN_COEX3 */ : PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
Still I have the follow-up question regarding how the CoEX is managed for M.2 WLAN + WWAN. […]
Got it. Thanks for the confirmation.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39115 )
Change subject: mb/google/dedede: Add WLAN configuration ......................................................................
Patch Set 11:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39115/11//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39115/11//COMMIT_MSG@7 PS11, Line 7: mb/google/dedede: Add WLAN configuration Configure WLAN
Hello Varshit B Pandya, build bot (Jenkins), Furquan Shaikh, Justin TerAvest, Aamir Bohra, Aamir Bohra, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39115
to look at the new patch set (#12).
Change subject: mb/google/dedede: Configure WLAN ......................................................................
mb/google/dedede: Configure WLAN
Turn on CNVi device. Turn on PCIe Root port that hosts WLAN device. Configure PCIe Clk Source and Clk Request mapping. Configure GPIOs used for WLAN - both CNVi and M.2.
BUG=None TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com Change-Id: I9bb8e57cdb688bc544929c94af380b9ef1d936a2 --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/baseboard/gpio.c M src/mainboard/google/dedede/variants/waddledoo/overridetree.cb 3 files changed, 35 insertions(+), 19 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/39115/12
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39115 )
Change subject: mb/google/dedede: Configure WLAN ......................................................................
Patch Set 12:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39115/11//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39115/11//COMMIT_MSG@7 PS11, Line 7: mb/google/dedede: Add WLAN configuration
Configure WLAN
Done
https://review.coreboot.org/c/coreboot/+/39115/5/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/39115/5/src/mainboard/google/dedede... PS5, Line 154: PAD_CFG_GPI_SCI_LOW
So if I understand correctly it is a way for WLAN connector to interrupt AP regarding some data is r […]
Done
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39115 )
Change subject: mb/google/dedede: Configure WLAN ......................................................................
Patch Set 12: Code-Review+2
I am unsure about the COEX pins, but rest of the CL LGTM.
Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39115 )
Change subject: mb/google/dedede: Configure WLAN ......................................................................
mb/google/dedede: Configure WLAN
Turn on CNVi device. Turn on PCIe Root port that hosts WLAN device. Configure PCIe Clk Source and Clk Request mapping. Configure GPIOs used for WLAN - both CNVi and M.2.
BUG=None TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com Change-Id: I9bb8e57cdb688bc544929c94af380b9ef1d936a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39115 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/baseboard/gpio.c M src/mainboard/google/dedede/variants/waddledoo/overridetree.cb 3 files changed, 35 insertions(+), 19 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 5a635b3..9a8ad66 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -84,12 +84,14 @@ register "PcieRpEnable[4]" = "0" register "PcieRpEnable[5]" = "0" register "PcieRpEnable[6]" = "0" - register "PcieRpEnable[7]" = "0" + # PCIe Root Port 8 (index 7) hosts M.2 E-key WLAN. + register "PcieRpEnable[7]" = "1"
register "PcieClkSrcUsage[0]" = "0xff" register "PcieClkSrcUsage[1]" = "0xff" register "PcieClkSrcUsage[2]" = "0xff" - register "PcieClkSrcUsage[3]" = "0xff" + # PCIe Clock Source 4 (index 3) is used by WLAN on PCIe Root Port 8 (index 7) + register "PcieClkSrcUsage[3]" = "7" register "PcieClkSrcUsage[4]" = "0xff" register "PcieClkSrcUsage[5]" = "0xff"
@@ -222,7 +224,10 @@ end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 off end # PMC SRAM - device pci 14.3 off end # CNVi wifi + chip drivers/intel/wifi + register "wake" = "GPE0_PME_B0" + device pci 14.3 on end # CNVi wifi + end device pci 14.5 off end # SDCard device pci 15.0 on end # I2C 0 device pci 15.1 on end # I2C 1 @@ -240,11 +245,12 @@ device pci 1c.0 off end # PCI Express Root Port 1 device pci 1c.1 off end # PCI Express Root Port 2 device pci 1c.2 off end # PCI Express Root Port 3 - device pci 1c.3 off end # PCI Express Root Port 4 - WLAN + device pci 1c.3 off end # PCI Express Root Port 4 device pci 1c.4 off end # PCI Express Root Port 5 device pci 1c.5 off end # PCI Express Root Port 6 device pci 1c.6 off end # PCI Express Root Port 7 - device pci 1c.7 off end # PCI Express Root Port 8 + # External PCIe port 4 is mapped to PCIe Root port 8 + device pci 1c.7 on end # PCI Express Root Port 8 - WLAN device pci 1e.0 off end # UART 0 device pci 1e.1 off end # UART 1 device pci 1e.2 on diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index 20c7be9..13419b8 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -64,8 +64,8 @@ PAD_NC(GPP_B6, NONE), /* B7 : PCIE_CLKREQ2_N */ PAD_NC(GPP_B7, NONE), - /* B8 : PCIE_CLKREQ3_N */ - PAD_NC(GPP_B8, NONE), + /* B8 : WLAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* B9 : PCIE_CLKREQ4_N */ PAD_NC(GPP_B9, NONE), /* B10 : PCIE_CLKREQ5_N */ @@ -149,11 +149,11 @@ /* D0 : WWAN_HOST_WAKE */ PAD_NC(GPP_D0, NONE), /* D1 : WLAN_PERST_L */ - PAD_NC(GPP_D1, NONE), + PAD_CFG_GPO(GPP_D1, 1, DEEP), /* D2 : WLAN_INT_L */ PAD_NC(GPP_D2, NONE), /* D3 : WLAN_PCIE_WAKE_ODL */ - PAD_NC(GPP_D3, NONE), + PAD_CFG_GPI_SCI_LOW(GPP_D3, NONE, DEEP, EDGE_SINGLE), /* D4 : TOUCH_INT_ODL */ PAD_NC(GPP_D4, NONE), /* D5 : TOUCH_RESET_L */ @@ -185,11 +185,11 @@ /* D18 : I2S_MCLK */ PAD_NC(GPP_D18, NONE), /* D19 : WWAN_WLAN_COEX1 */ - PAD_NC(GPP_D19, NONE), + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* D20 : WWAN_WLAN_COEX2 */ - PAD_NC(GPP_D20, NONE), + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* D21 : WWAN_WLAN_COEX3 */ - PAD_NC(GPP_D21, NONE), + PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), /* D22 : AP_I2C_SUB_SDA*/ PAD_NC(GPP_D22, NONE), /* D23 : AP_I2C_SUB_SCL */ @@ -236,17 +236,17 @@ /* E19 : GPP_E19/IMGCLKOUT_5/PCIE_LNK_DOWN */ PAD_NC(GPP_E19, NONE), /* E20 : CNV_BRI_DT_R */ - PAD_NC(GPP_E20, NONE), + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* E21 : CNV_BRI_RSP */ - PAD_NC(GPP_E21, NONE), + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* E22 : CNV_RGI_DT_R */ - PAD_NC(GPP_E22, NONE), + PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1), /* E23 : CNV_RGI_RSP */ - PAD_NC(GPP_E23, NONE), + PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1),
/* F4 : CNV_RF_RST_L */ - PAD_NC(GPP_F4, NONE), + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* F7 : EMMC_CMD */ PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), /* F8 : EMMC_DATA0 */ @@ -294,7 +294,7 @@ /* H1 : EN_PP3300_SD_U */ PAD_NC(GPP_H1, NONE), /* H2 : CNV_CLKREQ0 */ - PAD_NC(GPP_H2, NONE), + PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), /* H3 : GPP_H03/SX_EXIT_HOLDOFF_N */ PAD_NC(GPP_H3, NONE), /* H4 : AP_I2C_TS_SDA */ @@ -326,7 +326,7 @@ /* H17 : WWAN_RST_L */ PAD_NC(GPP_H17, NONE), /* H18 : WLAN_DISABLE_L */ - PAD_NC(GPP_H18, NONE), + PAD_CFG_GPO(GPP_H18, 1, DEEP), /* H19 : BT_DISABLE_L */ PAD_CFG_GPO(GPP_H19, 1, DEEP),
@@ -410,6 +410,9 @@ /* C5 : RAM_STRAP_3 */ PAD_CFG_GPI(GPP_C5, NONE, DEEP),
+ /* D1 : WLAN_PERST_L */ + PAD_CFG_GPO(GPP_D1, 1, DEEP), + /* H19 : BT_DISABLE_L */ PAD_CFG_GPO(GPP_H19, 0, DEEP), }; diff --git a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb index 061a0f8..9860e3d 100644 --- a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb @@ -49,5 +49,12 @@ device i2c 15 on end end end #I2C 0 + + device pci 1c.7 on + chip drivers/intel/wifi + register "wake" = "GPE0_DW2_03" + device pci 00.0 on end + end + end # PCI Express Root Port 8 - WLAN end end
-
Aamir Bohra (Code Review) -
Furquan Shaikh (Code Review)
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Karthik Ramasubramanian (Code Review)
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Martin Roth (Code Review)
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Paul Menzel (Code Review)
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Tim Wawrzynczak (Code Review)
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Varshit B Pandya (Code Review)