Change in coreboot[master]: mb/google/guybrush: Add SoC thermal zone

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Raul Rangel, Furquan Shaikh, Martin Roth, Rob Barnes.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54134 )

Change subject: mb/google/guybrush: Add SoC thermal zone
......................................................................

Patch Set 1:

(1 comment)

File src/mainboard/google/guybrush/variants/baseboard/devicetree.cb:

https://review.coreboot.org/c/coreboot/+/54134/comment/5f0d9de1_8738e0e6 
PS1, Line 55: chip drivers/acpi/thermal_zone
            : 		register "name" = ""SOC""
            : 
            : 		register "temperature_sensor_id" = "0"
            : 
            : 		register "polling_period" = "10000"
            : 
            : 		# EC is configured to power off the system at 92C, so add one degree of buffer
            : 		# so the OS can gracefully shutdown
            : 		register "critical_temperature" = "91"
            : 
            : 		# EC is configured to assert PROCHOT at 90C. That drastically lowers
            : 		# performance. Instead we will tell the OS to start throttling the CPUs at
            : 		# 85C in hopes that we don't hit the PROCHOT limit.
            : 		register "passive_config" = "{
            : 			.temperature = 85,
            : 			.time_constant_1 = 2,
            : 			.time_constant_2 = 5,
            : 			.time_sampling_period = 2000,
            : 		}"
            : 
            : 		device generic 0 on end
            : 	end
> Sorry if I wasn't clear. I meant a new callback.

Sorry I don't follow what the additional callback is for...

You could still support multiple controllers with an array, e.g.:

```

#define MAX_TEMP_CONTROLLERS 4

struct drivers_acpi_thermal_zone_config {
    /* Name of the thermal zone */
    const char *name;
        ...
        DEVTREE_CONST struct device *temp_controllers[MAX_TEMP_CONTROLLERS];
```

```
chip drivers/acpi/thermal_zone
        use chrome_ec as temp_controller[0]
        use temp_cntrl1 as temp_controller[1]
        register "name" = ""SOC""
        ...
end
...
device ref foobar alias temp_cntrl1 on end
device ref lpc_bridge on
        chip ec/google/chromeec
                device pnp 0c09.0 alias chrome_ec on end
        end
end
```