Change in coreboot[master]: soc/intel/common/block/gpio: add code for NMI enabling

[Michael Niewöhner (Code Review)]

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48090 )

Change subject: soc/intel/common/block/gpio: add code for NMI enabling
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Patch Set 10:

(2 comments)

https://review.coreboot.org/c/coreboot/+/48090/10/src/soc/intel/skylake/acpi... 
File src/soc/intel/skylake/acpi.c:

https://review.coreboot.org/c/coreboot/+/48090/10/src/soc/intel/skylake/acpi... 
PS10, Line 526: 1)
> always LINT1?

yes, see IOAPIC spec

https://review.coreboot.org/c/coreboot/+/48090/10/src/soc/intel/skylake/acpi... 
PS10, Line 526: 5,
> will this always be active-high, edge-triggered?

mh, LINT1 is a ISA interrupt (see IOAPIC spec) - and ISA interrupts are always edge/active-high according to the ACPI spec