Change in coreboot[master]: mb/siemens/mc_ehl2: Disable PCI clock outputs on XIO bridge

[Mario Scheithauer (Code Review)]

Attention is currently required from: Mario Scheithauer.
Hello build bot (Jenkins), Werner Zeh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/63931

to look at the new patch set (#5).

Change subject: mb/siemens/mc_ehl2: Disable PCI clock outputs on XIO bridge
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mb/siemens/mc_ehl2: Disable PCI clock outputs on XIO bridge

On this mainboard there are legacy PCI devices connected behind a
PCIe-2-PCI bridge. Not all clock outputs of this bridge are used. This
patch disables the unused PCI clock outputs on the XIO2001 bridge.

Change-Id: Iedbf0abfa554e0a6ad5b1d1741f4e9934103d171
Signed-off-by: Mario Scheithauer 
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M src/mainboard/siemens/mc_ehl/variants/mc_ehl2/mainboard.c
1 file changed, 8 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/63931/5