Change in coreboot[master]: soc/intel/mtl: Do initial Meteor Lake SoC commit till bootblock

[Ravishankar Sarawadi (Code Review)]

Attention is currently required from: Felix Singer, Jamie Ryu, Subrata Banik, Wonkyu Kim, Ethan Tsao, Tim Wawrzynczak, Paul Menzel, Angel Pons, Raj Astekar, Ravishankar Sarawadi.
Ravishankar Sarawadi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62772 )

Change subject: soc/intel/mtl: Do initial Meteor Lake SoC commit till bootblock
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Patch Set 14:

(3 comments)

File src/soc/intel/meteorlake/Kconfig:

https://review.coreboot.org/c/coreboot/+/62772/comment/72a338ea_22ca15e0 
PS13, Line 51: Platform FSP integration guide document
> Not yet, so keeping it same as ADL for now.

Done

File src/soc/intel/meteorlake/include/soc/iomap.h:

https://review.coreboot.org/c/coreboot/+/62772/comment/837060f2_6fb5db40 
PS13, Line 63: 
             : #define IOE_PCR_ABOVE_4G_BASE_ADDR	0x3fff0000000
             : #define IOE_P2SB_BAR		IOE_PCR_ABOVE_4G_BASE_ADDR
             : #define IOE_P2SB_SIZE		(256 * MiB)
             : 
             : #define IOM_BASE_ADDR		0x3fff0aa0000
             : #define IOM_BASE_SIZE		0x1600
             : #define IOM_BASE_ADDR_MAX	0x3fff0aa15ff
> Yes, for TCSS functionality based on IOE.

Done

File src/soc/intel/meteorlake/include/soc/pci_devs.h:

https://review.coreboot.org/c/coreboot/+/62772/comment/daaa52ca_77358ca6 
PS13, Line 186: //#define PCH_DEV_SLOT_LPC	PCI_DEV_SLOT_ESPI
> Right, it's not needed.

Done