[M] Change in coreboot[main]: drivers/intel/fsp2_0: Add limited to 32-bits FSP 2.4 support

[Jérémy Compostella (Code Review)]

Attention is currently required from: Andrey Petrov, Bora Guvendik, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Nick Vaccaro, Ronak Kanabar, Subrata Banik, Tarun, Wonkyu Kim.

Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80275?usp=email )

Change subject: drivers/intel/fsp2_0: Add limited to 32-bits FSP 2.4 support
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Patch Set 7:

(5 comments)

Patchset:

PS3:
> > > quick feedback […]

I updated the commit message to clarify the document references better. I am working on the `TEST` flag.

Patchset:

PS7: 
I think I got all almost all your points right. Thanks for reviewing so promptly 😊
I am still working on the `TEST` flag even though obviously I am testing.

File src/drivers/intel/fsp2_0/memory_init.c:

https://review.coreboot.org/c/coreboot/+/80275/comment/3652cc48_f387451b :
PS3, Line 295: 
             : #if CONFIG(PLATFORM_USES_FSP2_4)
> i don't believe u need this. we don't see this inside silicon_init. […]

Done

https://review.coreboot.org/c/coreboot/+/80275/comment/1d7cf690_c157d465 :
PS3, Line 297: multi_phase_init
> > Considering we are in memory_init. […]

Done

https://review.coreboot.org/c/coreboot/+/80275/comment/50dc9ee6_2322241b :
PS3, Line 437: 	if (hdr->fsp_multi_phase_mem_init_entry_offset)
> > Wouldn't it be dangerous to look outside after the limit of the data structure ? These fields are  […]

Done