Change in coreboot[master]: src/soc/intel/common/itss: Add support to get IRQ configuration for P...

[Aamir Bohra (Code Review)]

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34089 )

Change subject: src/soc/intel/common/itss: Add support to get IRQ configuration for PCI devices
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Patch Set 20:

(1 comment)

https://review.coreboot.org/c/coreboot/+/34089/20/src/soc/intel/common/block... 
File src/soc/intel/common/block/itss/irq.c:

https://review.coreboot.org/c/coreboot/+/34089/20/src/soc/intel/common/block... 
PS20, Line 50: irq_entry->int_line = int_line++;
> > The IRQ assignments for F0:f7 can range from 16:23(shareable IRQs, expect for LPSS controllers), c […]

the implementation currently maps only one intline to a intpin eg 16-INTA, 17-INTB and so on..

/* Assign INTA, INTB, INTC, INTD */
irq_entry->int_pin = (irq_entry->int_line % 4) + 1;