John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44501 )
Change subject: mb/google/volteer: Configure GPP_A19 and GPP_A20 as PAD_NC ......................................................................
mb/google/volteer: Configure GPP_A19 and GPP_A20 as PAD_NC
GPP_A19(DP_HPD1) and GPP_A20(DP_HPD2) were configured native function (NF1) without internal pull-down which wrongly presents HPD interrupts. DP_HPD had been removed for EVT design as those events are through eSPI. This change configures GPP_A19 and GPP_A20 to be no connection.
BUG=b:162566436 TEST=Booted to kernel and verified no kernel HPD pins assertion message on Voteer EVT board.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: Ia3245741b776b75073d2b43d36c8ea40b476b3ed --- M src/mainboard/google/volteer/variants/volteer2/gpio.c 1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/44501/1
diff --git a/src/mainboard/google/volteer/variants/volteer2/gpio.c b/src/mainboard/google/volteer/variants/volteer2/gpio.c index 96d940a..ceb5e1f 100644 --- a/src/mainboard/google/volteer/variants/volteer2/gpio.c +++ b/src/mainboard/google/volteer/variants/volteer2/gpio.c @@ -19,9 +19,9 @@ /* A18 : DDSP_HPDB ==> HDMI_HPD */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* A19 : DDSP_HPD1 ==> USB_C0_DP_HPD */ - PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), + PAD_NC(GPP_A19, NONE), /* A20 : DDSP_HPD2 ==> USB_C1_DP_HPD */ - PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), + PAD_NC(GPP_A20, NONE), /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */ PAD_CFG_GPO(GPP_A21, 1, DEEP), /* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */
Chiranjeevi Rapolu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44501 )
Change subject: mb/google/volteer: Configure GPP_A19 and GPP_A20 as PAD_NC ......................................................................
Patch Set 1: Code-Review+1
Do we need similar change for Voxel too? With this, I no longer see those kernel DP-HDP related prints.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44501 )
Change subject: mb/google/volteer: Configure GPP_A19 and GPP_A20 as PAD_NC ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44501/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44501/1//COMMIT_MSG@16 PS1, Line 16: Voteer Volteer
Hello build bot (Jenkins), Shaunak Saha, Wonkyu Kim, Eric Herrmann, Ravishankar Sarawadi, Tim Wawrzynczak, Chiranjeevi Rapolu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44501
to look at the new patch set (#2).
Change subject: mb/google/volteer: Configure GPP_A19 and GPP_A20 as PAD_NC ......................................................................
mb/google/volteer: Configure GPP_A19 and GPP_A20 as PAD_NC
GPP_A19(DP_HPD1) and GPP_A20(DP_HPD2) were configured native function (NF1) without internal pull-down which wrongly presents HPD interrupts. DP_HPD had been removed for EVT design as those events are through eSPI. This change configures GPP_A19 and GPP_A20 to be no connection.
BUG=b:162566436 TEST=Booted to kernel and verified no kernel HPD pins assertion message on Volteer EVT board.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: Ia3245741b776b75073d2b43d36c8ea40b476b3ed --- M src/mainboard/google/volteer/variants/volteer2/gpio.c 1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/44501/2
John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44501 )
Change subject: mb/google/volteer: Configure GPP_A19 and GPP_A20 as PAD_NC ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44501/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44501/1//COMMIT_MSG@16 PS1, Line 16: Voteer
Volteer
Done
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44501 )
Change subject: mb/google/volteer: Configure GPP_A19 and GPP_A20 as PAD_NC ......................................................................
Patch Set 2:
Native function pin mux for DPs are done by FSP after pin mux by gpio.c So, we also need to configure below in overridetree.cb for not confuring DP_HPD1 and DP_HPD2. register "DdiPort1Hpd" = "0" register "DdiPort2Hpd" = "0" Note that these are enabled in devicetree.cb in baseboard.
Hello build bot (Jenkins), Shaunak Saha, Wonkyu Kim, Eric Herrmann, Ravishankar Sarawadi, Tim Wawrzynczak, Chiranjeevi Rapolu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44501
to look at the new patch set (#3).
Change subject: mb/google/volteer: Configure DP_HPD as PAD_NC and disable DdiPortHpd ......................................................................
mb/google/volteer: Configure DP_HPD as PAD_NC and disable DdiPortHpd
GPP_A19(DP_HPD1) and GPP_A20(DP_HPD2) were configured native function (NF1) without internal pull-down which wrongly presents HPD interrupts. DP_HPD had been removed for EVT design as those events are through eSPI. This change configures GPP_A19 and GPP_A20 to be no connection and disables DdiPort1Hpd and DdiPort2Hpd.
BUG=b:162566436 TEST=Booted to kernel and verified no kernel HPD pins assertion message on Voteer EVT board.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: Ia3245741b776b75073d2b43d36c8ea40b476b3ed --- M src/mainboard/google/volteer/variants/volteer2/gpio.c M src/mainboard/google/volteer/variants/volteer2/overridetree.cb 2 files changed, 5 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/44501/3
Hello build bot (Jenkins), Shaunak Saha, Wonkyu Kim, Eric Herrmann, Ravishankar Sarawadi, Tim Wawrzynczak, Chiranjeevi Rapolu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44501
to look at the new patch set (#4).
Change subject: mb/google/volteer: Configure DP_HPD as PAD_NC and disable DdiPortHpd ......................................................................
mb/google/volteer: Configure DP_HPD as PAD_NC and disable DdiPortHpd
GPP_A19(DP_HPD1) and GPP_A20(DP_HPD2) were configured native function (NF1) without internal pull-down which wrongly presents HPD interrupts. DP_HPD had been removed for EVT design as those events are through eSPI. This change configures GPP_A19 and GPP_A20 to be no connection and disables DdiPort1Hpd and DdiPort2Hpd.
BUG=b:162566436 TEST=Booted to kernel and verified no kernel HPD pins assertion message on Voteer EVT board.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: Ia3245741b776b75073d2b43d36c8ea40b476b3ed --- M src/mainboard/google/volteer/variants/volteer2/gpio.c M src/mainboard/google/volteer/variants/volteer2/overridetree.cb 2 files changed, 4 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/44501/4
John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44501 )
Change subject: mb/google/volteer: Configure DP_HPD as PAD_NC and disable DdiPortHpd ......................................................................
Patch Set 4:
Patch Set 2:
Native function pin mux for DPs are done by FSP after pin mux by gpio.c So, we also need to configure below in overridetree.cb for not confuring DP_HPD1 and DP_HPD2. register "DdiPort1Hpd" = "0" register "DdiPort2Hpd" = "0" Note that these are enabled in devicetree.cb in baseboard.
done.
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44501 )
Change subject: mb/google/volteer: Configure DP_HPD as PAD_NC and disable DdiPortHpd ......................................................................
Patch Set 4: Code-Review+2
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44501 )
Change subject: mb/google/volteer: Configure DP_HPD as PAD_NC and disable DdiPortHpd ......................................................................
Patch Set 4: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/44501/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44501/4//COMMIT_MSG@17 PS4, Line 17: Voteer Volteer 😉
Hello build bot (Jenkins), Shaunak Saha, Wonkyu Kim, Eric Herrmann, Ravishankar Sarawadi, Tim Wawrzynczak, Chiranjeevi Rapolu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44501
to look at the new patch set (#5).
Change subject: mb/google/volteer: Configure DP_HPD as PAD_NC and disable DdiPortHpd ......................................................................
mb/google/volteer: Configure DP_HPD as PAD_NC and disable DdiPortHpd
GPP_A19(DP_HPD1) and GPP_A20(DP_HPD2) were configured native function (NF1) without internal pull-down which wrongly presents HPD interrupts. DP_HPD had been removed for EVT design as those events are through eSPI. This change configures GPP_A19 and GPP_A20 to be no connection and disables DdiPort1Hpd and DdiPort2Hpd.
BUG=b:162566436 TEST=Booted to kernel and verified no kernel HPD pins assertion message on Volteer EVT board.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: Ia3245741b776b75073d2b43d36c8ea40b476b3ed --- M src/mainboard/google/volteer/variants/volteer2/gpio.c M src/mainboard/google/volteer/variants/volteer2/overridetree.cb 2 files changed, 4 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/44501/5
John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44501 )
Change subject: mb/google/volteer: Configure DP_HPD as PAD_NC and disable DdiPortHpd ......................................................................
Patch Set 5:
(1 comment)
Patch Set 2:
Native function pin mux for DPs are done by FSP after pin mux by gpio.c So, we also need to configure below in overridetree.cb for not confuring DP_HPD1 and DP_HPD2. register "DdiPort1Hpd" = "0" register "DdiPort2Hpd" = "0" Note that these are enabled in devicetree.cb in baseboard.
https://review.coreboot.org/c/coreboot/+/44501/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44501/4//COMMIT_MSG@17 PS4, Line 17: Voteer
Volteer 😉
Done
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44501 )
Change subject: mb/google/volteer: Configure DP_HPD as PAD_NC and disable DdiPortHpd ......................................................................
Patch Set 5: Code-Review+2
Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44501 )
Change subject: mb/google/volteer: Configure DP_HPD as PAD_NC and disable DdiPortHpd ......................................................................
mb/google/volteer: Configure DP_HPD as PAD_NC and disable DdiPortHpd
GPP_A19(DP_HPD1) and GPP_A20(DP_HPD2) were configured native function (NF1) without internal pull-down which wrongly presents HPD interrupts. DP_HPD had been removed for EVT design as those events are through eSPI. This change configures GPP_A19 and GPP_A20 to be no connection and disables DdiPort1Hpd and DdiPort2Hpd.
BUG=b:162566436 TEST=Booted to kernel and verified no kernel HPD pins assertion message on Volteer EVT board.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: Ia3245741b776b75073d2b43d36c8ea40b476b3ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/44501 Reviewed-by: Caveh Jalali caveh@chromium.org Reviewed-by: Wonkyu Kim wonkyu.kim@intel.com Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/volteer/variants/volteer2/gpio.c M src/mainboard/google/volteer/variants/volteer2/overridetree.cb 2 files changed, 4 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Caveh Jalali: Looks good to me, approved Wonkyu Kim: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/google/volteer/variants/volteer2/gpio.c b/src/mainboard/google/volteer/variants/volteer2/gpio.c index 09a4dd5..7b14646 100644 --- a/src/mainboard/google/volteer/variants/volteer2/gpio.c +++ b/src/mainboard/google/volteer/variants/volteer2/gpio.c @@ -19,9 +19,9 @@ /* A18 : DDSP_HPDB ==> HDMI_HPD */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* A19 : DDSP_HPD1 ==> USB_C0_DP_HPD */ - PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), + PAD_NC(GPP_A19, NONE), /* A20 : DDSP_HPD2 ==> USB_C1_DP_HPD */ - PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), + PAD_NC(GPP_A20, NONE), /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */ PAD_CFG_GPO(GPP_A21, 1, DEEP), /* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */ diff --git a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb index 76a5b87..3036a48 100644 --- a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb @@ -2,6 +2,8 @@ register "TcssAuxOri" = "1" register "IomTypeCPortPadCfg[0]" = "0x090E000A" register "IomTypeCPortPadCfg[1]" = "0x090E000D" + register "DdiPort1Hpd" = "0" + register "DdiPort2Hpd" = "0"
device domain 0 on device pci 15.0 on
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Caveh Jalali (Code Review) -
Chiranjeevi Rapolu (Code Review)
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John Zhao (Code Review)
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Tim Wawrzynczak (Code Review)
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Wonkyu Kim (Code Review)