Change in coreboot[master]: soc/intel/tgl: Enable Tracehub (not to be merged)

[Shreesh Chhabbi (Code Review)]

Shreesh Chhabbi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42397 )

Change subject: soc/intel/tgl: Enable Tracehub (not to be merged)
......................................................................

soc/intel/tgl: Enable Tracehub (not to be merged)

Change-Id: I288c17c0a3258cd506cac23014aac5e7520143b2
Signed-off-by: Shreesh Chhabbi 
---
M src/soc/intel/tigerlake/fsp_params.c
M src/soc/intel/tigerlake/romstage/fsp_params.c
2 files changed, 18 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/42397/1

diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index b9dbec8..7450c34 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -80,14 +80,19 @@
 {
    int i;
    FSP_S_CONFIG *params = &supd->FspsConfig;
+	unsigned int  *tracehub_mem;

struct device *dev;
    struct soc_intel_tigerlake_config *config;
    config = config_of_soc();

+	tracehub_mem = malloc(4*1024*sizeof(uint32_t));
+
    /* Parse device tree and enable/disable Serial I/O devices */
    parse_devicetree(params);

+	params->TraceHubMemBase = (UINT32) tracehub_mem;
+
    /* Load VBT before devicetree-specific config. */
    params->GraphicsConfigPtr = (uintptr_t)vbt_get();

diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c
index f7956c8..b58952f 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params.c
@@ -18,6 +18,9 @@
    unsigned int i;
    uint32_t mask = 0;
    const struct device *dev;
+	//uint32_t  *tracehub_mem;
+
+	//tracehub_mem = malloc(4*1024*sizeof(uint32_t));

dev = pcidev_path_on_root(SA_DEVFN_IGD);
    if (!dev || !dev->enabled) {
@@ -196,6 +199,16 @@

/* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */
    m_cfg->VmxEnable = CONFIG(ENABLE_VMX);
+	//m_cfg->TraceHubMemBase = tracehub_mem;
+	m_cfg->DciEn = 1;
+	m_cfg->DciDbcMode = 0;
+	m_cfg->CpuTraceHubMode = 2;
+	m_cfg->CpuTraceHubMemReg0Size = 2;
+	m_cfg->CpuTraceHubMemReg1Size = 2;
+	m_cfg->PchTraceHubMode = 2;
+	m_cfg->PchTraceHubMemReg0Size = 2;
+	m_cfg->PchTraceHubMemReg1Size = 2;
+	m_cfg->PlatformDebugConsent = 2;
 }

void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)

[S] Change in coreboot[master]: soc/intel/tgl: Enable Tracehub (not to be merged)

[Stefan Reinauer (Code Review)]

Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/42397?usp=email )

Change subject: soc/intel/tgl: Enable Tracehub (not to be merged)
......................................................................

Abandoned