Change in coreboot[master]: soc/intel/cannonlake_rvp: Enable low power S0 Idle capability

[Vaibhav Shankar (Code Review)]

Vaibhav Shankar has uploaded this change for review. ( https://review.coreboot.org/25291

Change subject: soc/intel/cannonlake_rvp: Enable low power S0 Idle capability
......................................................................

soc/intel/cannonlake_rvp: Enable low power S0 Idle capability

This patch sets the ACPI FADT flag ACPI_FADT_LOW_POWER_S0
if S0ix is enabled for the platform.

TEST= Boot to OS and check the ACPI_FADT_LOW_PWR_IDLE_S0 flag
      is set in FACP table - FADT.Flags[21] bit.

Change-Id: I50245de95c9024b8a2fecba95772d25feba21446
Signed-off-by: Vaibhav Shankar 
---
M src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
M src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
M src/soc/intel/cannonlake/acpi.c
3 files changed, 9 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/25291/1

diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
index 3e60ed9..cb80deb 100644
--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
@@ -70,6 +70,9 @@
    # GPIO for SD card detect
    register "sdcard_cd_gpio" = "GPP_G5"

+	#Enable S0ix
+	register "s0ix_enable" = "1"
+
    # Audio
    register "i2c[3]" = "{
    	.speed = I2C_SPEED_STANDARD,
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
index 8502048..24d25ec 100644
--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
@@ -68,6 +68,9 @@
    # GPIO for SD card detect
    register "sdcard_cd_gpio" = "GPP_G5"

+	#Enable S0ix
+	register "s0ix_enable" = "1"
+
    device domain 0 on
    	device pci 00.0 on  end # Host Bridge
    	device pci 02.0 on  end # Integrated Graphics Device
diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c
index 9dcaa33..0134b86 100644
--- a/src/soc/intel/cannonlake/acpi.c
+++ b/src/soc/intel/cannonlake/acpi.c
@@ -187,6 +187,9 @@
    fadt->x_pm_tmr_blk.resv = 0;
    fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR;
    fadt->x_pm_tmr_blk.addrh = 0x0;
+
+	if(config->s0ix_enable)
+		fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0;
 }
 uint32_t soc_read_sci_irq_select(void)
 {