New patch to review for coreboot: nb/amd/mct_ddr3: Restore MCA settings immediately after frequency switch

[Timothy Pearson]

Timothy Pearson ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14442

-gerrit

commit b97d630be5b5098794a98b69de49ed61eab45c4b
Author: Timothy Pearson 
Date:   Wed Apr 20 17:05:26 2016 -0500

nb/amd/mct_ddr3: Restore MCA settings immediately after frequency switch

Certain configurations of RDIMMs on specific mainboards tend to cause
    early training errors, which if uncaught lead to instability and hard
    deadlock later in ramstage.  These early training errors interfere
    with RDIMM register programming, but are normally detected as parity
    issues by the MCA.

Now that coreboot can automatically restart on MCE, reconfigure
    the MCE sync flood logic immediately after frequency change is complete.

Change-Id: I112d0c26a7b1310afc6f1198987fac1f542f54f9
    Signed-off-by: Timothy Pearson 
---
 src/northbridge/amd/amdmct/mct_ddr3/mct_d.c    | 9 +++++++++
 src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 9 ---------
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
index 3582efa..9d501b6 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
@@ -8084,6 +8084,15 @@ void mct_SetDramConfigHi_D(struct MCTStatStruc *pMCTstat,
    pci_write_config32(pDCTstat->dev_nbmisc, 0x48, 0x0);
    pci_write_config32(pDCTstat->dev_nbmisc, 0x4c, 0x0);

+	/* Restore MCA settings */
+	if (pDCTstat->mca_config_backed_up) {
+		dword = pci_read_config32(pDCTstat->dev_nbmisc, 0x44);
+		dword |= (pDCTstat->sync_flood_on_dram_err & 0x1) << 30;
+		dword |= (pDCTstat->sync_flood_on_any_uc_err & 0x1) << 21;
+		dword |= (pDCTstat->sync_flood_on_uc_dram_ecc_err & 0x1) << 2;
+		pci_write_config32(pDCTstat->dev_nbmisc, 0x44, dword);
+	}
+
    printk(BIOS_DEBUG, "%s: Done\n", __func__);
 }

diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
index 203d112..65de0f8 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
@@ -264,15 +264,6 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
    			/* Clear MC4 error status */
    			pci_write_config32(pDCTstat->dev_nbmisc, 0x48, 0x0);
    			pci_write_config32(pDCTstat->dev_nbmisc, 0x4c, 0x0);
-
-				/* Restore MCA settings */
-				if (pDCTstat->mca_config_backed_up) {
-					val = pci_read_config32(pDCTstat->dev_nbmisc, 0x44);
-					val |= (pDCTstat->sync_flood_on_dram_err & 0x1) << 30;
-					val |= (pDCTstat->sync_flood_on_any_uc_err & 0x1) << 21;
-					val |= (pDCTstat->sync_flood_on_uc_dram_ecc_err & 0x1) << 2;
-					pci_write_config32(pDCTstat->dev_nbmisc, 0x44, val);
-				}
    		}
    	}
    }