Change in coreboot[master]: vc/intel/fsp/fsp2_0/cooperlake_sp: Fix WW47 FSP Memory map HOB mismatch
Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48228 )
Change subject: vc/intel/fsp/fsp2_0/cooperlake_sp: Fix WW47 FSP Memory map HOB mismatch ......................................................................
vc/intel/fsp/fsp2_0/cooperlake_sp: Fix WW47 FSP Memory map HOB mismatch
Tested=On OCP Delta Lake, verify the memory map hob data are correct.
Change-Id: I7bb2e9f41daa4cbce49169535eadf7f0d4972716 Signed-off-by: Johnny Lin johnny_lin@wiwynn.com --- M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/48228/1
diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h index 53b7305..598d78c 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h @@ -159,7 +159,7 @@ UINT8 NumChPerMC; UINT8 numberEntries; // Number of Memory Map Elements SYSTEM_MEMORY_MAP_ELEMENT Element[(MAX_SOCKET * MAX_DRAM_CLUSTERS * MAX_SAD_RULES) + MAX_FPGA_REMOTE_SAD_RULES]; - UINT8 reserved5[2216]; + UINT8 reserved5[2249]; MEMMAP_SOCKET Socket[MAX_SOCKET]; UINT8 reserved6[1603];
Hello Marc Jones, Jonathan Zhang, Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48228
to look at the new patch set (#2).
Change subject: vc/intel/fsp/fsp2_0/cooperlake_sp: Update WW47 FSP Memory map HOB ......................................................................
vc/intel/fsp/fsp2_0/cooperlake_sp: Update WW47 FSP Memory map HOB
Tested=On OCP Delta Lake, verify the memory map hob data are correct.
Change-Id: I7bb2e9f41daa4cbce49169535eadf7f0d4972716 Signed-off-by: Johnny Lin johnny_lin@wiwynn.com --- M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/48228/2
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48228 )
Change subject: vc/intel/fsp/fsp2_0/cooperlake_sp: Update WW47 FSP Memory map HOB ......................................................................
Patch Set 2: Code-Review+2
We will get Intel to do a major cleanup for HOB header file composition in SPR-SP FSP...
Marc Jones has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48228 )
Change subject: vc/intel/fsp/fsp2_0/cooperlake_sp: Update WW47 FSP Memory map HOB ......................................................................
Patch Set 2:
Patch Set 2: Code-Review+2
We will get Intel to do a major cleanup for HOB header file composition in SPR-SP FSP...
Did the version checks go in? This should be updated with a FSP version update.
Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48228 )
Change subject: vc/intel/fsp/fsp2_0/cooperlake_sp: Update WW47 FSP Memory map HOB ......................................................................
Patch Set 2:
Patch Set 2:
Patch Set 2: Code-Review+2
We will get Intel to do a major cleanup for HOB header file composition in SPR-SP FSP...
Did the version checks go in? This should be updated with a FSP version update.
No. Intel (Nate) advised us not to do version check based on build number which contains WW. So Intel has to revisit their verisoning method for CPX-SP FSP, then we can do corresponding coreboot work.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48228 )
Change subject: vc/intel/fsp/fsp2_0/cooperlake_sp: Update WW47 FSP Memory map HOB ......................................................................
Patch Set 2: Code-Review+2
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48228 )
Change subject: vc/intel/fsp/fsp2_0/cooperlake_sp: Update WW47 FSP Memory map HOB ......................................................................
vc/intel/fsp/fsp2_0/cooperlake_sp: Update WW47 FSP Memory map HOB
Tested=On OCP Delta Lake, verify the memory map hob data are correct.
Change-Id: I7bb2e9f41daa4cbce49169535eadf7f0d4972716 Signed-off-by: Johnny Lin johnny_lin@wiwynn.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/48228 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Jonathan Zhang jonzhang@fb.com Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h 1 file changed, 1 insertion(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Jonathan Zhang: Looks good to me, approved
diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h index 53b7305..598d78c 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h @@ -159,7 +159,7 @@ UINT8 NumChPerMC; UINT8 numberEntries; // Number of Memory Map Elements SYSTEM_MEMORY_MAP_ELEMENT Element[(MAX_SOCKET * MAX_DRAM_CLUSTERS * MAX_SAD_RULES) + MAX_FPGA_REMOTE_SAD_RULES]; - UINT8 reserved5[2216]; + UINT8 reserved5[2249]; MEMMAP_SOCKET Socket[MAX_SOCKET]; UINT8 reserved6[1603];
-
Angel Pons (Code Review) -
Johnny Lin (Code Review)
-
Jonathan Zhang (Code Review)
-
Marc Jones (Code Review)