Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54035 )
Change subject: Doc/nb/intel/sandybridge: Fix up some typos and cosmetics ......................................................................
Doc/nb/intel/sandybridge: Fix up some typos and cosmetics
Change-Id: I23b0c94ec9881aef8e39a14bc048856a65a6286d Signed-off-by: Angel Pons th3fanbus@gmail.com --- M Documentation/northbridge/intel/sandybridge/index.md M Documentation/northbridge/intel/sandybridge/nri.md M Documentation/northbridge/intel/sandybridge/nri_registers.md 3 files changed, 5 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/54035/1
diff --git a/Documentation/northbridge/intel/sandybridge/index.md b/Documentation/northbridge/intel/sandybridge/index.md index c1d4b99..27fbb2cc2 100644 --- a/Documentation/northbridge/intel/sandybridge/index.md +++ b/Documentation/northbridge/intel/sandybridge/index.md @@ -4,6 +4,6 @@
## Topics
-- [Native Ram Initialization](nri.md) +- [Native RAM Initialization](nri.md) - [RAM initialization feature matrix](nri_features.md) - [ME Cleaner](me_cleaner.md) diff --git a/Documentation/northbridge/intel/sandybridge/nri.md b/Documentation/northbridge/intel/sandybridge/nri.md index 812cd23..bf0b89f 100644 --- a/Documentation/northbridge/intel/sandybridge/nri.md +++ b/Documentation/northbridge/intel/sandybridge/nri.md @@ -40,7 +40,7 @@ +---------+-------------------------------------------------------------------+------------+--------------+ ```
-## (Inoffical) register documentation +## (Unoffical) register documentation - [Sandy Bridge - Register documentation](nri_registers.md)
## Frequency selection @@ -83,7 +83,7 @@
**Note:** This feature is available since coreboot 4.4
### MRC cache -The name *MRC cache* might be missleading as in case of *Native ram init* +The name *MRC cache* might be misleading as in case of *Native RAM init* there's no MRC, but for historical reasons it's still named *MRC cache*. The MRC cache is part of flash memory that is writeable by coreboot. At the end of the boot process coreboot will write the RAM training results to diff --git a/Documentation/northbridge/intel/sandybridge/nri_registers.md b/Documentation/northbridge/intel/sandybridge/nri_registers.md index 8f85629..aae1205 100644 --- a/Documentation/northbridge/intel/sandybridge/nri_registers.md +++ b/Documentation/northbridge/intel/sandybridge/nri_registers.md @@ -1,9 +1,9 @@ -# Inoffical Documentation of Intel MCHBAR register space. +# Unofficial Documentation of Intel MCHBAR register space.
The MCHBAR can be enabled by using register 0x48 of PCI(0:0:0) device.
This documentation is incomplete and might be incorrect. -Please handle with care ! +Please handle with care!
**MCHBAR + 0x4**
-
Angel Pons (Code Review)