Change in coreboot[master]: soc/intel/common/cse: Add function to perform CSE lock configuration
Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Werner Zeh, Patrick Rudolph. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61520 )
Change subject: soc/intel/common/cse: Add function to perform CSE lock configuration ......................................................................
Patch Set 6:
(2 comments)
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/61520/comment/99626557_c7753ce9 PS5, Line 1014: /*
Ack ? Ack ?
means?
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/61520/comment/d294cf94_0f241b17 PS6, Line 1018: (cse_is_hfs1_com_normal() || cse_is_hfs1_com_soft_temp_disable())
Only BIOS should have capability to trigger global reset and sending GLOBAL RESET MEI message. […]
3rd para says. "Furthermore, if Intel® CSME is in ERROR state, **BIOS** can use I/O 0xCF9 write of >06h or 0Eh command with PMC PWRM offset 1048h register bit [20] CF9GR set to perform the global reset
I commented based on 3rd para you posted in this comment thread. Can you please create crosbug, we can discuss further there?
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Sridhar Siricilla (Code Review)