Change in coreboot[master]: src/soc/intel/commmon/itss: Add support to pass interrupt config to FSP

[Aamir Bohra (Code Review)]

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34089 )

Change subject: src/soc/intel/commmon/itss: Add support to pass interrupt config to FSP
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Patch Set 5:
> Patch Set 5:
>
> Why can't it be done in coreboot?
> It looks like src/soc/intel/skylake/lpc.c already has code that looks similar.

it is configuring just the PIRQ routing configuration. The PIRx registers are still getting programmed via FSP on passing the UPD from coreboot(skylake irq.c), I am trying to just pass that config as per the board device selection.