New patch to review for coreboot: intel/strago: Disable unused devices.

[Hannah Williams]

Hannah Williams ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13423

-gerrit

commit b4f9ef8dde54ecefc0ee169b82bd257d0c75c095
Author: Divagar Mohandass 
Date:   Mon Sep 21 11:51:07 2015 +0530

intel/strago: Disable unused devices.

This change will disable unused devices in
    device tree to improve boot performance.

TEST=Build/Flash CB and boot to OS.
    verify Touch screen, Audio, WIFI and Track pad functionality.

Change-Id: Ib5ae31c96d75f9a5b0f8d8b72d058e18fe7d7e67
    Signed-off-by: Divagar Mohandass 
    Original-Reviewed-on: https://chromium-review.googlesource.com/300943
    Original-Reviewed-by: Hannah Williams 
    Original-Reviewed-by: Aaron Durbin 
    Original-Tested-by: Gomathi Kumar 
---
 src/mainboard/intel/strago/devicetree.cb | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/src/mainboard/intel/strago/devicetree.cb b/src/mainboard/intel/strago/devicetree.cb
index b2d5115..9133787 100755
--- a/src/mainboard/intel/strago/devicetree.cb
+++ b/src/mainboard/intel/strago/devicetree.cb
@@ -29,11 +29,11 @@ chip soc/intel/braswell
    register "PcdEnableDma1" = "1"
    register "PcdEnableI2C0" = "1"
    register "PcdEnableI2C1" = "1"
-	register "PcdEnableI2C2" = "1"
-	register "PcdEnableI2C3" = "1"
+	register "PcdEnableI2C2" = "0"
+	register "PcdEnableI2C3" = "0"
    register "PcdEnableI2C4" = "1"
    register "PcdEnableI2C5" = "1"
-	register "PcdEnableI2C6" = "1"
+	register "PcdEnableI2C6" = "0"
    register "PunitPwrConfigDisable" = "0"	# Enable SVID
    register "ChvSvidConfig" = "SVID_PMIC_CONFIG"
    register "PcdEmmcMode" = "PCH_ACPI_MODE"
@@ -95,7 +95,7 @@ chip soc/intel/braswell
    				# EDS Table 24-4, Figure 24-5
    	device pci 00.0 on end	# 8086 2280 - SoC transaction router
    	device pci 02.0 on end	# 8086 22b0/22b1 - B1/C0 stepping Graphics and Display
-		device pci 03.0 on end	# 8086 22b8 - Camera and Image Processor
+		device pci 03.0 off end	# 8086 22b8 - Camera and Image Processor
    	device pci 0b.0 on end	# 8086 22dc - ?
    	device pci 10.0 on end	# 8086 2294 - MMC Port
    	device pci 11.0 off end	# 8086 0F15 - SDIO Port
@@ -107,25 +107,25 @@ chip soc/intel/braswell
    	device pci 18.0 on end	# 8086 22c0 - SIO - DMA
    	device pci 18.1 on end	# 8086 22c1 -   I2C Port 1
    	device pci 18.2 on end	# 8086 22c2 -   I2C Port 2
-		device pci 18.3 on end	# 8086 22c3 -   I2C Port 3
-		device pci 18.4 on end	# 8086 22c4 -   I2C Port 4
+		device pci 18.3 off end	# 8086 22c3 -   I2C Port 3
+		device pci 18.4 off end	# 8086 22c4 -   I2C Port 4
    	device pci 18.5 on end	# 8086 22c5 -   I2C Port 5
    	device pci 18.6 on end	# 8086 22c6 -   I2C Port 6
-		device pci 18.7 on end	# 8086 22c7 -   I2C Port 7
-		device pci 1a.0 on end	# 8086 0F18 - Trusted Execution Engine
+		device pci 18.7 off end	# 8086 22c7 -   I2C Port 7
+		device pci 1a.0 off end	# 8086 0F18 - Trusted Execution Engine
    	device pci 1b.0 on end	# 8086 0F04 - HD Audio
    	device pci 1c.0 on end	# 8086 0000 - PCIe Root Port 1
    	device pci 1c.1 on end	# 8086 0000 - PCIe Root Port 2
    	device pci 1c.2 on end	# 8086 0000 - PCIe Root Port 3
-		device pci 1c.3 on end	# 8086 0000 - PCIe Root Port 4
+		device pci 1c.3 off end	# 8086 0000 - PCIe Root Port 4
    	device pci 1e.0 on end	# 8086 2286 - SIO - DMA
    	device pci 1e.1 off end	# 8086 0F08 -   PWM 1
    	device pci 1e.2 off end	# 8086 0F09 -   PWM 2
    	device pci 1e.3 on end	# 8086 228a -   HSUART 1
-		device pci 1e.4 on end	# 8086 228c -   HSUART 2
+		device pci 1e.4 off end	# 8086 228c -   HSUART 2
    	device pci 1e.5 on end	# 8086 228e -   SPI 1
-		device pci 1e.6 on end	# 8086 2290 -   SPI 2
-		device pci 1e.7 on end	# 8086 22ac -   SPI 3
+		device pci 1e.6 off end	# 8086 2290 -   SPI 2
+		device pci 1e.7 off end	# 8086 22ac -   SPI 3
    	device pci 1f.0 on	# 8086 229c - LPC bridge
    		chip drivers/pc80/tpm
    			# Rising edge interrupt