Change in coreboot[master]: mb/intel/tglrvp: add Tiger Lake memory initialization support

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38998 )

Change subject: mb/intel/tglrvp: add Tiger Lake memory initialization support
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Patch Set 5:

(2 comments)

https://review.coreboot.org/c/coreboot/+/38998/5/src/soc/intel/tigerlake/inc... 
File src/soc/intel/tigerlake/include/soc/meminit_tgl.h:

PS5: 
Please separate out SoC and mainboard changes into different CLs.

https://review.coreboot.org/c/coreboot/+/38998/5/src/soc/intel/tigerlake/inc... 
PS5, Line 64: 
            : /* Rcomp configuration information */
            : struct rcomp_cfg {
            : 	/* Rcomp Resistor */
            : 	uint16_t rcomp_resistor;
            : 
            : 	/* Rcomp Target */
            : 	uint16_t rcomp_target[NUM_RCOMP_TARGETS];
            : 
            : };
            : 
Why is this required? IIUC, based on discussions on partner bug, Rcomp values are not required to be passed in.