Change in coreboot[master]: soc/intel/alderlake: Add (and fix) devices in IRQ table

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Patrick Rudolph.
Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56175 )

Change subject: soc/intel/alderlake: Add (and fix) devices in IRQ table
......................................................................

soc/intel/alderlake: Add (and fix) devices in IRQ table

Some devices were missing from the IRQ table, and this lack of
IRQ programming for the devices (although unused), was causing S0ix
entry to fail.

BUG=b:176858827
TEST=suspend_stress_test -c10 passes, EC observes SLP_S0IX# toggle
correctly upon entry/exit from S0ix

Signed-off-by: Tim Wawrzynczak 
Change-Id: Ia7612ee008842ba2b8dcd36deb201f4f26130660
---
M src/soc/intel/alderlake/fsp_params.c
1 file changed, 38 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/56175/1

diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index 5b0d631..5175cdc 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -80,9 +80,34 @@
    	},
    },
    {
+		.slot = SA_DEV_SLOT_GNA,
+		.fns = {
+			ANY_PIRQ(SA_DEVFN_GNA),
+		},
+	},
+	{
    	.slot = SA_DEV_SLOT_TCSS,
    	.fns = {
    		ANY_PIRQ(SA_DEVFN_TCSS_XHCI),
+			ANY_PIRQ(SA_DEVFN_TCSS_XDCI),
+		},
+	},
+	{
+		.slot = PCH_DEV_SLOT_SIO0,
+		.fns = {
+			DIRECT_IRQ(PCH_DEVFN_I2C6),
+			DIRECT_IRQ(PCH_DEVFN_I2C7),
+			ANY_PIRQ(PCH_DEVFN_THC0),
+			ANY_PIRQ(PCH_DEVFN_THC1),
+		},
+	},
+	{
+		.slot = PCH_DEV_SLOT_SIO6,
+		.fns = {
+			DIRECT_IRQ(PCH_DEVFN_UART3),
+			DIRECT_IRQ(PCH_DEVFN_UART4),
+			DIRECT_IRQ(PCH_DEVFN_UART5),
+			DIRECT_IRQ(PCH_DEVFN_UART6),
    	},
    },
    {
@@ -90,12 +115,23 @@
    	.fns = {
    		DIRECT_IRQ(PCH_DEVFN_ISH),
    		DIRECT_IRQ(PCH_DEVFN_GSPI2),
+			ANY_PIRQ(PCH_DEVFN_UFS),
+		},
+	},
+	{
+		.slot = PCH_DEV_SLOT_SIO2,
+		.fns = {
+			DIRECT_IRQ(PCH_DEVFN_GSPI3),
+			DIRECT_IRQ(PCH_DEVFN_GSPI4),
+			DIRECT_IRQ(PCH_DEVFN_GSPI5),
+			DIRECT_IRQ(PCH_DEVFN_GSPI6),
    	},
    },
    {
    	.slot = PCH_DEV_SLOT_XHCI,
    	.fns = {
    		ANY_PIRQ(PCH_DEVFN_XHCI),
+			DIRECT_IRQ(PCH_DEVFN_USBOTG),
    		ANY_PIRQ(PCH_DEVFN_CNVI_WIFI),
    	},
    },
@@ -160,8 +196,8 @@
    	.fns = {
    		FIXED_INT_ANY_PIRQ(PCH_DEVFN_UART0, PCI_INT_A),
    		FIXED_INT_ANY_PIRQ(PCH_DEVFN_UART1, PCI_INT_B),
-			ANY_PIRQ(PCH_DEVFN_GSPI0),
-			ANY_PIRQ(PCH_DEVFN_GSPI1),
+			DIRECT_IRQ(PCH_DEVFN_GSPI0),
+			DIRECT_IRQ(PCH_DEVFN_GSPI1),
    	},
    },
    {