Change in coreboot[master]: soc/intel/tigerlake: Allow devicetree to fill UPD related to TCSS OC - coreboot-gerrit

14 May 2021


      Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Zhuohao Lee, Patrick Rudolph.
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54075 )
Change subject: soc/intel/tigerlake: Allow devicetree to fill UPD related to TCSS OC
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Patch Set 1:
(1 comment)
File src/soc/intel/tigerlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/54075/comment/ffa3a119_6b8c1861 
PS1, Line 275: config->tcss_ports[i].ocpin;
...
If it's 96-column limit, checkpatch needs to be fixed. […]
Ack
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I5058a18b1f4d11701cebbba85734fbc279539e52
Gerrit-Change-Number: 54075
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