Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44072 )
Change subject: [WIP] soc/intel/baytrail: Add libgfxinit support ......................................................................
[WIP] soc/intel/baytrail: Add libgfxinit support
Tested on Asrock Q1900M, lights up.
Change-Id: I7c8beea3fc94bd2da94a0caa77dcc1c749c778aa Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/drivers/intel/gma/Kconfig M src/soc/intel/baytrail/gfx.c M src/soc/intel/baytrail/romstage/gfx.c 3 files changed, 13 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/44072/1
diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig index c515888..811f59b 100644 --- a/src/drivers/intel/gma/Kconfig +++ b/src/drivers/intel/gma/Kconfig @@ -80,7 +80,7 @@ def_bool y depends on NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_X4X \ || NORTHBRIDGE_INTEL_IRONLAKE || NORTHBRIDGE_INTEL_SANDYBRIDGE \ - || NORTHBRIDGE_INTEL_HASWELL \ + || NORTHBRIDGE_INTEL_HASWELL || SOC_INTEL_BAYTRAIL \ || SOC_INTEL_BROADWELL || SOC_INTEL_SKYLAKE || SOC_INTEL_APOLLOLAKE \ || SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE \ || SOC_INTEL_WHISKEYLAKE @@ -109,6 +109,7 @@ config GFX_GMA_GENERATION string default "Broxton" if SOC_INTEL_APOLLOLAKE + default "Valleyview" if SOC_INTEL_BAYTRAIL default "Skylake" if SOC_INTEL_SKYLAKE || SOC_INTEL_KABYLAKE || \ SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE default "Haswell" if NORTHBRIDGE_INTEL_HASWELL || SOC_INTEL_BROADWELL diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c index 0ee3cef..9062585 100644 --- a/src/soc/intel/baytrail/gfx.c +++ b/src/soc/intel/baytrail/gfx.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
+#include <bootmode.h> #include <device/mmio.h> #include <device/pci_ops.h> #include <console/console.h> @@ -7,6 +8,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <drivers/intel/gma/opregion.h> +#include <drivers/intel/gma/libgfxinit.h> #include <reg_script.h> #include <soc/gfx.h> #include <soc/iosf.h> @@ -362,8 +364,14 @@
gfx_panel_setup(dev);
- /* Run VBIOS */ - pci_dev_init(dev); + if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) { + int lightup_ok; + gma_gfxinit(&lightup_ok); + gfx_set_init_done(lightup_ok); + } else { + /* Run VBIOS */ + pci_dev_init(dev); + }
/* Post VBIOS Init */ gfx_post_vbios_init(dev); diff --git a/src/soc/intel/baytrail/romstage/gfx.c b/src/soc/intel/baytrail/romstage/gfx.c index eb0b5e7..c8fac9d 100644 --- a/src/soc/intel/baytrail/romstage/gfx.c +++ b/src/soc/intel/baytrail/romstage/gfx.c @@ -21,7 +21,7 @@
ggc &= ~(GGC_GTT_SIZE_MASK | GGC_GSM_SIZE_MASK); /* 32MB GSM is not supported with <C0 stepping. */ - ggc |= GGC_GTT_SIZE_2MB | GGC_GSM_SIZE_64MB; + ggc |= GGC_GTT_SIZE_2MB | GGC_GSM_SIZE_128MB; /* Enable VGA decoding as well. */ ggc &= ~(GGC_VGA_DISABLE);
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44072
to look at the new patch set (#6).
Change subject: soc/intel/baytrail: Add libgfxinit support ......................................................................
soc/intel/baytrail: Add libgfxinit support
Tested on not-yet-merged Asrock Q1900M, lights up.
Change-Id: I7c8beea3fc94bd2da94a0caa77dcc1c749c778aa Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/drivers/intel/gma/Kconfig M src/soc/intel/baytrail/gfx.c 2 files changed, 12 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/44072/6
Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/44072?usp=email )
Change subject: soc/intel/baytrail: Add libgfxinit support ......................................................................
Abandoned
This patch has not been touched in over 12 months. Anyone who wants to take over work on this patch, please feel free to restore it and do any work needed to get it merged. If you create a new patch based on this work, please credit the original author.
-
Angel Pons (Code Review) -
Martin L Roth (Code Review)