Attention is currently required from: Ravi kumar, Sajida Bhanu, Paul Menzel. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55376 )
Change subject: spi: Limit the SPI NOR size ......................................................................
Patch Set 10:
(1 comment)
Patchset:
PS1:
Hi Julius, […]
Yes, this patch as you uploaded here is unacceptable. If you go the route I described and don't change the coreboot FMAP, there will be no actual flash accesses beyond 8MB... depthcharge is just written to require space to buffer the whole flash in case it is needed, but if the FMAP doesn't place anything there it won't actually touch it. That's the best I can offer you. If your hardware team is still worried that this doesn't match the behavior of a real Chromebook closely enough, please ask them to build a board where the hardware actually matches a real Chromebook as well. (Also, FWIW, if you follow the discussion at b/191969933 it seems quite likely that we'll have to upgrade the real Chromebook to 16MB at some point as well, at least for some variants. Flash size can change between variants, that's a regular thing and no big deal. Just make sure the hardware is accurately represented by the code so it doesn't get confused.)
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Julius Werner (Code Review)