Change in coreboot[master]: mb/razer/blade_stealth_kbl: Configure IRQs as level triggered for HID...

[Karthik Ramasubramanian (Code Review)]

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50453 )

Change subject: mb/razer/blade_stealth_kbl: Configure IRQs as level triggered for HID over I2C
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mb/razer/blade_stealth_kbl: Configure IRQs as level triggered for HID over I2C

As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4,
the interrupt line used by the device is required to be level triggered.
Hence, this change updates the configuration of the HID over I2C devices
to be level triggered.

References:
[1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d...

BUG=b:172846122
TEST=./util/abuild/abuild

Change-Id: Ifdc3f061d919c8db9001c7a4cc26eb21117958d7
Signed-off-by: Karthikeyan Ramasubramanian 
---
M src/mainboard/razer/blade_stealth_kbl/devicetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/50453/1

diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb
index 44b3523..a358fb8 100644
--- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb
+++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb
@@ -191,7 +191,7 @@
    		chip drivers/i2c/hid
    			register "generic.hid" = ""PNP0C50""
    			register "generic.desc" = ""Synaptics Touchpad""
-				register "generic.irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_E7_IRQ)"
+				register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E7_IRQ)"
    			register "generic.probed" = "1"
    			register "hid_desc_reg_offset" = "0x20"
    			device i2c 0x2c on end