New patch to review for coreboot: 9bf1b2b mainboard/asus/k8v-x: Abstract PNP programming to obj level

[Edward O'Callaghan]

Edward O'Callaghan ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5730

-gerrit

commit 9bf1b2b97a42dd19afc21ec568b245a3c0822d54
Author: Edward O'Callaghan 
Date:   Wed May 14 03:41:00 2014 +1000

mainboard/asus/k8v-x: Abstract PNP programming to obj level

This board #include's fragments of superio support leading to a blur of
    abstraction even at the source level. Convert serial init to recent
    general winbond romstage framework. Ensure superio code and romstage
    code are separated down to the object level.

Change-Id: Ibedc147761caacfae9136d77af7179f22f1f147e
    Signed-off-by: Edward O'Callaghan 
---
 src/mainboard/asus/k8v-x/romstage.c | 22 ++++++++++++----------
 1 file changed, 12 insertions(+), 10 deletions(-)

diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c
index 4fe1016..0ab882f 100644
--- a/src/mainboard/asus/k8v-x/romstage.c
+++ b/src/mainboard/asus/k8v-x/romstage.c
@@ -6,6 +6,7 @@
  * Copyright (C) 2006 MSI
  * (Written by Bingxun Shi  for MSI)
  * Copyright (C) 2007 Rudolf Marek 
+ * Copyright (C) 2014 Edward O'Callaghan 
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -38,7 +39,8 @@ unsigned int get_sbdn(unsigned bus);
 #include "cpu/x86/lapic.h"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/early_ht.c"
-#include "superio/winbond/w83697hf/early_serial.c"
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83697hf/w83697hf.h>
 #include "southbridge/via/vt8237r/early_smbus.c"
 #include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */
 #include "cpu/x86/bist.h"
@@ -97,8 +99,12 @@ unsigned int get_sbdn(unsigned bus)
 static void sio_init(void)
 {
    u8 reg;
+	u16 port = SERIAL_DEV >> 8;
+
+	/* enter SIO PNP config state */
+	outb(0x87, port);
+	outb(0x87, port);

-	pnp_enter_ext_func_mode(SERIAL_DEV);
    reg = pnp_read_config(SERIAL_DEV, 0x24);
    /* 4 Mbit flash */
    reg = (reg & ~0x30) | 0x20;
@@ -107,6 +113,9 @@ static void sio_init(void)
    /* enable MEMW#, so flash can be written */
    reg |= 0x08;
    pnp_write_config(SERIAL_DEV, 0x24, reg);
+
+	/* exit SIO PNP config state */
+	outb(0xAA, port);
 }

void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
@@ -124,7 +133,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
    struct sys_info *sysinfo = &sysinfo_car;

sio_init();
-	w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
    console_init();
    enable_rom_decode();

@@ -137,13 +146,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
    	enumerate_ht_chain();
    }

-	// FIXME why is this executed again? --->
-	sio_init();
-	w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-	console_init();
-	enable_rom_decode();
-	// <--- FIXME why is this executed again?
-
    print_info("now booting... real_main\n");

if (bist == 0)