Change in coreboot[master]: soc/amd/common/block/psp/psp_gen2: simplify soc_read_c2p38

[Felix Held (Code Review)]

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64078 )

Change subject: soc/amd/common/block/psp/psp_gen2: simplify soc_read_c2p38
......................................................................

soc/amd/common/block/psp/psp_gen2: simplify soc_read_c2p38

Commit 198cc26e4951b3dbca588286706b7df562c45d42 (soc/amd/common/block/
psp/psp_gen2: use SMN access to PSP) changed how the PSP registers are
accessed. Since the new method doesn't need to rely on a MMIO base
address to be configured, the read will always be successful and so
soc_read_c2p38 doesn't need to return an error status and can directly
return the value instead.

Signed-off-by: Felix Held 
Change-Id: I1abace04668947ba3223a107461a27dddc0a9d83
---
M src/soc/amd/common/block/psp/psp_def.h
M src/soc/amd/common/block/psp/psp_gen2.c
2 files changed, 4 insertions(+), 11 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/64078/1

diff --git a/src/soc/amd/common/block/psp/psp_def.h b/src/soc/amd/common/block/psp/psp_def.h
index 4d860ff..d1a06fb 100644
--- a/src/soc/amd/common/block/psp/psp_def.h
+++ b/src/soc/amd/common/block/psp/psp_def.h
@@ -86,6 +86,6 @@
 /* This command needs to be implemented by the generation specific code. */
 int send_psp_command(u32 command, void *buffer);

-enum cb_err soc_read_c2p38(uint32_t *msg_38_value);
+uint32_t soc_read_c2p38(void);

#endif /* __AMD_PSP_DEF_H__ */
diff --git a/src/soc/amd/common/block/psp/psp_gen2.c b/src/soc/amd/common/block/psp/psp_gen2.c
index 820d44d..208a9bf 100644
--- a/src/soc/amd/common/block/psp/psp_gen2.c
+++ b/src/soc/amd/common/block/psp/psp_gen2.c
@@ -111,10 +111,9 @@
    return 0;
 }

-enum cb_err soc_read_c2p38(uint32_t *msg_38_value)
+uint32_t soc_read_c2p38(void)
 {
-	*msg_38_value = smn_read32(SMN_PSP_PUBLIC_BASE + CORE_2_PSP_MSG_38_OFFSET);
-	return CB_SUCCESS;
+	return smn_read32(SMN_PSP_PUBLIC_BASE + CORE_2_PSP_MSG_38_OFFSET);
 }

static void psp_set_spl_fuse(void *unused)
@@ -122,7 +121,6 @@
    if (!CONFIG(SOC_AMD_COMMON_BLOCK_PSP_FUSE_SPL))
    	return;

-	uint32_t msg_38_value = 0;
    int cmd_status = 0;
    struct mbox_cmd_late_spl_buffer buffer = {
    	.header = {
@@ -130,12 +128,7 @@
    	}
    };

-	if (soc_read_c2p38(&msg_38_value) != CB_SUCCESS) {
-		printk(BIOS_ERR, "PSP: Failed to read psp base address.\n");
-		return;
-	}
-
-	if (msg_38_value & CORE_2_PSP_MSG_38_FUSE_SPL) {
+	if (soc_read_c2p38() & CORE_2_PSP_MSG_38_FUSE_SPL) {
    	printk(BIOS_DEBUG, "PSP: Fuse SPL requested\n");
    	cmd_status = send_psp_command(MBOX_BIOS_CMD_SET_SPL_FUSE, &buffer);
    	psp_print_cmd_status(cmd_status, NULL);