Change in coreboot[master]: soc/intel/alderlake: Add support for ADL-N PCH

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59752 )

Change subject: soc/intel/alderlake: Add support for ADL-N PCH
......................................................................

soc/intel/alderlake: Add support for ADL-N PCH

Introduce the `SOC_INTEL_ALDERLAKE_PCH_N` Kconfig option and use it to
specify the correct amount of PCIe I/O.

Document number 645550 indicates that Alder Lake-N has 12 PCH root ports
and no CPU root ports.

Document number 645548 indicates ADL-N has 5 clock sources and 5 clock
request signals.

Signed-off-by: Usha P 
Change-Id: I7ebbcdcdb1ccc34b80ec71ac3e591fe4ad6b1904
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59752
Tested-by: build bot (Jenkins) 
Reviewed-by: Subrata Banik 
Reviewed-by: Kangheui Won 
Reviewed-by:  Felix Singer 
Reviewed-by: Tim Wawrzynczak 
---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/include/soc/bootblock.h
2 files changed, 11 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Subrata Banik: Looks good to me, approved
   Felix Singer: Looks good to me, but someone else must approve
  Tim Wawrzynczak: Looks good to me, approved
  Kangheui Won: Looks good to me, but someone else must approve

diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 2f8f3da..9fe2668 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -11,6 +11,12 @@
    help
      Choose this option if your mainboard has a PCH-M chipset.

+config SOC_INTEL_ALDERLAKE_PCH_N
+	bool
+	select SOC_INTEL_ALDERLAKE
+	help
+	  Choose this option if your mainboard has a PCH-N chipset.
+
 config SOC_INTEL_ALDERLAKE_PCH_P
    bool
    select SOC_INTEL_ALDERLAKE
@@ -178,11 +184,13 @@
 config MAX_PCH_ROOT_PORTS
    int
    default 10 if SOC_INTEL_ALDERLAKE_PCH_M
+	default 12 if SOC_INTEL_ALDERLAKE_PCH_N
    default 12 if SOC_INTEL_ALDERLAKE_PCH_P

config MAX_CPU_ROOT_PORTS
    int
    default 1 if SOC_INTEL_ALDERLAKE_PCH_M
+	default 0 if SOC_INTEL_ALDERLAKE_PCH_N
    default 3 if SOC_INTEL_ALDERLAKE_PCH_P

config MAX_ROOT_PORTS
@@ -192,11 +200,13 @@
 config MAX_PCIE_CLOCK_SRC
    int
    default 6 if SOC_INTEL_ALDERLAKE_PCH_M
+	default 5 if SOC_INTEL_ALDERLAKE_PCH_N
    default 7 if SOC_INTEL_ALDERLAKE_PCH_P

config MAX_PCIE_CLOCK_REQ
    int
    default 6  if SOC_INTEL_ALDERLAKE_PCH_M
+	default 5  if SOC_INTEL_ALDERLAKE_PCH_N
    default 10 if SOC_INTEL_ALDERLAKE_PCH_P

config SMM_TSEG_SIZE
diff --git a/src/soc/intel/alderlake/include/soc/bootblock.h b/src/soc/intel/alderlake/include/soc/bootblock.h
index 059568d..ce2e42e 100644
--- a/src/soc/intel/alderlake/include/soc/bootblock.h
+++ b/src/soc/intel/alderlake/include/soc/bootblock.h
@@ -4,6 +4,7 @@
 #define _SOC_ALDERLAKE_BOOTBLOCK_H_

#if	CONFIG(SOC_INTEL_ALDERLAKE_PCH_M) +	\
+	CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) +	\
    CONFIG(SOC_INTEL_ALDERLAKE_PCH_P) != 1
 #error "Please select exactly one PCH type"
 #endif