Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31652
Change subject: getac/p470: Let clang-format handle the coding style ......................................................................
getac/p470: Let clang-format handle the coding style
Also make the format mandatory for the board.
Change-Id: Ib34af7c4db359e132b968fe8409580af05fba9e3 Signed-off-by: Patrick Georgi pgeorgi@google.com --- A .clang-format-scope M src/mainboard/getac/p470/acpi_tables.c M src/mainboard/getac/p470/cstates.c M src/mainboard/getac/p470/ec_oem.c M src/mainboard/getac/p470/ec_oem.h M src/mainboard/getac/p470/gpio.c M src/mainboard/getac/p470/hda_verb.c M src/mainboard/getac/p470/irq_tables.c M src/mainboard/getac/p470/mainboard.c M src/mainboard/getac/p470/mainboard.h M src/mainboard/getac/p470/mptable.c M src/mainboard/getac/p470/romstage.c M src/mainboard/getac/p470/smihandler.c 13 files changed, 179 insertions(+), 136 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/31652/1
diff --git a/.clang-format-scope b/.clang-format-scope new file mode 100644 index 0000000..96c588c --- /dev/null +++ b/.clang-format-scope @@ -0,0 +1 @@ +src/mainboard/getac diff --git a/src/mainboard/getac/p470/acpi_tables.c b/src/mainboard/getac/p470/acpi_tables.c index 162c20a..460f345 100644 --- a/src/mainboard/getac/p470/acpi_tables.c +++ b/src/mainboard/getac/p470/acpi_tables.c @@ -33,7 +33,7 @@ gnvs->cmbp = 0x00; }
-static long acpi_create_ecdt(acpi_ecdt_t * ecdt) +static long acpi_create_ecdt(acpi_ecdt_t *ecdt) { /* Attention: Make sure these match the values from * the DSDT's ec.asl @@ -43,7 +43,7 @@
acpi_header_t *header = &(ecdt->header);
- memset((void *) ecdt, 0, ecdt_len); + memset((void *)ecdt, 0, ecdt_len);
/* fill out header fields */ memcpy(header->signature, "ECDT", 4); @@ -61,7 +61,7 @@ ecdt->ec_control.addrl = 0x66; ecdt->ec_control.addrh = 0;
- ecdt->ec_data.space_id = ACPI_ADDRESS_SPACE_IO; /* Memory */ + ecdt->ec_data.space_id = ACPI_ADDRESS_SPACE_IO; /* Memory */ ecdt->ec_data.bit_width = 8; ecdt->ec_data.bit_offset = 0; ecdt->ec_data.addrl = 0x62; @@ -73,14 +73,12 @@
strncpy((char *)ecdt->ec_id, ec_id, strlen(ec_id));
- header->checksum = - acpi_checksum((void *) ecdt, ecdt_len); + header->checksum = acpi_checksum((void *)ecdt, ecdt_len);
return header->length; }
-unsigned long mainboard_write_acpi_tables(struct device *device, - unsigned long start, +unsigned long mainboard_write_acpi_tables(struct device *device, unsigned long start, acpi_rsdp_t *rsdp) { unsigned long current; diff --git a/src/mainboard/getac/p470/cstates.c b/src/mainboard/getac/p470/cstates.c index 38b0d30..2f1f815 100644 --- a/src/mainboard/getac/p470/cstates.c +++ b/src/mainboard/getac/p470/cstates.c @@ -16,21 +16,21 @@ #include <southbridge/intel/i82801gx/i82801gx.h>
static acpi_cstate_t cst_entries[] = { - { - /* ACPI C1 / CPU C1 */ - 1, 0x01, 1000, - { ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0, 0 } - }, - { - /* ACPI C2 / CPU C2 */ - 2, 0x01, 500, - { ACPI_ADDRESS_SPACE_IO, 8, 0, { 0 }, DEFAULT_PMBASE + LV2, 0 } - }, - { - /* ACPI C3 / CPU C2 */ - 2, 0x11, 250, - { ACPI_ADDRESS_SPACE_IO, 8, 0, { 0 }, DEFAULT_PMBASE + LV3, 0 } - }, + {/* ACPI C1 / CPU C1 */ + 1, + 0x01, + 1000, + {ACPI_ADDRESS_SPACE_FIXED, 1, 2, {1}, 0, 0}}, + {/* ACPI C2 / CPU C2 */ + 2, + 0x01, + 500, + {ACPI_ADDRESS_SPACE_IO, 8, 0, {0}, DEFAULT_PMBASE + LV2, 0}}, + {/* ACPI C3 / CPU C2 */ + 2, + 0x11, + 250, + {ACPI_ADDRESS_SPACE_IO, 8, 0, {0}, DEFAULT_PMBASE + LV3, 0}}, };
int get_cst_entries(acpi_cstate_t **entries) diff --git a/src/mainboard/getac/p470/ec_oem.c b/src/mainboard/getac/p470/ec_oem.c index 8740167..49b7274 100644 --- a/src/mainboard/getac/p470/ec_oem.c +++ b/src/mainboard/getac/p470/ec_oem.c @@ -32,7 +32,7 @@ } if (!timeout) { printk(BIOS_DEBUG, "Timeout while sending OEM command 0x%02x to EC!\n", - command); + command); // return -1; }
@@ -51,8 +51,7 @@ printk(BIOS_SPEW, "."); } if (!timeout) { - printk(BIOS_DEBUG, "Timeout while sending OEM data 0x%02x to EC!\n", - data); + printk(BIOS_DEBUG, "Timeout while sending OEM data 0x%02x to EC!\n", data); // return -1; }
@@ -112,12 +111,18 @@ { u8 ec_sc = inb(EC_OEM_SC); printk(BIOS_DEBUG, "Embedded Controller Status: "); - if (ec_sc & (1 << 6)) printk(BIOS_DEBUG, "SMI_EVT "); - if (ec_sc & (1 << 5)) printk(BIOS_DEBUG, "SCI_EVT "); - if (ec_sc & (1 << 4)) printk(BIOS_DEBUG, "BURST "); - if (ec_sc & (1 << 3)) printk(BIOS_DEBUG, "CMD "); - if (ec_sc & (1 << 1)) printk(BIOS_DEBUG, "IBF "); - if (ec_sc & (1 << 0)) printk(BIOS_DEBUG, "OBF "); + if (ec_sc & (1 << 6)) + printk(BIOS_DEBUG, "SMI_EVT "); + if (ec_sc & (1 << 5)) + printk(BIOS_DEBUG, "SCI_EVT "); + if (ec_sc & (1 << 4)) + printk(BIOS_DEBUG, "BURST "); + if (ec_sc & (1 << 3)) + printk(BIOS_DEBUG, "CMD "); + if (ec_sc & (1 << 1)) + printk(BIOS_DEBUG, "IBF "); + if (ec_sc & (1 << 0)) + printk(BIOS_DEBUG, "OBF "); printk(BIOS_DEBUG, "\n");
return ec_sc; diff --git a/src/mainboard/getac/p470/ec_oem.h b/src/mainboard/getac/p470/ec_oem.h index 5d56107..ba42d7e 100644 --- a/src/mainboard/getac/p470/ec_oem.h +++ b/src/mainboard/getac/p470/ec_oem.h @@ -17,23 +17,35 @@ #ifndef _MAINBOARD_EC_OEM_H #define _MAINBOARD_EC_OEM_H
-#define EC_OEM_DATA 0x68 -#define EC_OEM_SC 0x6c +#define EC_OEM_DATA 0x68 +#define EC_OEM_SC 0x6c
/* EC_SC input */ -#define EC_SMI_EVT (1 << 6) // 1: SMI event pending -#define EC_SCI_EVT (1 << 5) // 1: SCI event pending -#define EC_BURST (1 << 4) // controller is in burst mode -#define EC_CMD (1 << 3) // 1: byte in data register is command - // 0: byte in data register is data -#define EC_IBF (1 << 1) // 1: input buffer full (data ready for ec) -#define EC_OBF (1 << 0) // 1: output buffer full (data ready for host) +// 1: SMI event pending +#define EC_SMI_EVT (1 << 6) + +// 1: SCI event pending +#define EC_SCI_EVT (1 << 5) + +// controller is in burst mode +#define EC_BURST (1 << 4) + +// 1: byte in data register is command +// 0: byte in data register is data +#define EC_CMD (1 << 3) + +// 1: input buffer full (data ready for ec) +#define EC_IBF (1 << 1) + +// 1: output buffer full (data ready for host) +#define EC_OBF (1 << 0) + /* EC_SC output */ -#define RD_EC 0x80 // Read Embedded Controller -#define WR_EC 0x81 // Write Embedded Controller -#define BE_EC 0x82 // Burst Enable Embedded Controller -#define BD_EC 0x83 // Burst Disable Embedded Controller -#define QR_EC 0x84 // Query Embedded Controller +#define RD_EC 0x80 // Read Embedded Controller +#define WR_EC 0x81 // Write Embedded Controller +#define BE_EC 0x82 // Burst Enable Embedded Controller +#define BD_EC 0x83 // Burst Disable Embedded Controller +#define QR_EC 0x84 // Query Embedded Controller
int send_ec_oem_command(u8 command); int send_ec_oem_data(u8 data); diff --git a/src/mainboard/getac/p470/gpio.c b/src/mainboard/getac/p470/gpio.c index be52a86..2785bca 100644 --- a/src/mainboard/getac/p470/gpio.c +++ b/src/mainboard/getac/p470/gpio.c @@ -74,8 +74,7 @@ .gpio8 = GPIO_INVERT, };
-static const struct pch_gpio_set1 pch_gpio_set1_blink = { -}; +static const struct pch_gpio_set1 pch_gpio_set1_blink = {};
static const struct pch_gpio_set2 pch_gpio_set2_mode = { .gpio33 = GPIO_MODE_GPIO, @@ -100,16 +99,18 @@ };
const struct pch_gpio_map mainboard_gpio_map = { - .set1 = { - .mode = &pch_gpio_set1_mode, - .direction = &pch_gpio_set1_direction, - .level = &pch_gpio_set1_level, - .blink = &pch_gpio_set1_blink, - .invert = &pch_gpio_set1_invert, - }, - .set2 = { - .mode = &pch_gpio_set2_mode, - .direction = &pch_gpio_set2_direction, - .level = &pch_gpio_set2_level, - }, + .set1 = + { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + }, + .set2 = + { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, }; diff --git a/src/mainboard/getac/p470/hda_verb.c b/src/mainboard/getac/p470/hda_verb.c index e858a35..1ec2205 100644 --- a/src/mainboard/getac/p470/hda_verb.c +++ b/src/mainboard/getac/p470/hda_verb.c @@ -17,9 +17,9 @@
const u32 cim_verb_data[] = { /* coreboot specific header */ - 0x10ec0262, // Codec Vendor / Device ID: Realtek ALC262 - 0x10714700, // Subsystem ID - 0x0000000d, // Number of jacks + 0x10ec0262, // Codec Vendor / Device ID: Realtek ALC262 + 0x10714700, // Subsystem ID + 0x0000000d, // Number of jacks
/* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10ec0000 */ AZALIA_SUBVENDOR(0x0, 0x10EC0000), diff --git a/src/mainboard/getac/p470/irq_tables.c b/src/mainboard/getac/p470/irq_tables.c index 06d1492..fa491bf 100644 --- a/src/mainboard/getac/p470/irq_tables.c +++ b/src/mainboard/getac/p470/irq_tables.c @@ -17,18 +17,19 @@ #include <arch/pirq_routing.h>
static const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total 18 devices on the bus */ - 0x00, /* Where the interrupt router lies (bus) */ - (0x1f << 3)|0x0, /* Where the interrupt router lies (dev) */ - 0, /* IRQs devoted exclusively to PCI usage */ - 0x8086, /* Vendor */ - 0x27b0, /* Device */ - 0, /* miniport */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0xf, /* u8 checksum. */ + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* There can be total 18 devices on the bus */ + 0x00, /* Where the interrupt router lies (bus) */ + (0x1f << 3) | 0x0, /* Where the interrupt router lies (dev) */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x27b0, /* Device */ + 0, /* miniport */ + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ + 0xf, /* u8 checksum. */ { + // clang-format off /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ {0x00,(0x01 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // PCIe? {0x00,(0x02 << 3)|0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // VGA @@ -48,8 +49,8 @@ {0x01,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x0, 0x0}, // Ethernet 8168 {0x02,(0x00 << 3)|0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0x0dcd8}}, 0x9, 0x0}, {0x03,(0x00 << 3)|0x0, {{0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcd8}, {0x60, 0x0dcf8}}, 0xa, 0x0}, - } -}; + // clang-format on + }};
unsigned long write_pirq_routing_table(unsigned long addr) { diff --git a/src/mainboard/getac/p470/mainboard.c b/src/mainboard/getac/p470/mainboard.c index 5d271fd..0645424 100644 --- a/src/mainboard/getac/p470/mainboard.c +++ b/src/mainboard/getac/p470/mainboard.c @@ -25,7 +25,7 @@
#include "mainboard.h"
-#define MAX_LCD_BRIGHTNESS 0xd8 +#define MAX_LCD_BRIGHTNESS 0xd8
static void ec_enable(void) { @@ -77,7 +77,8 @@ static void mainboard_init(struct device *dev) { ec_enable(); - install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_TXT_STRETCH, 0, 3); + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_TXT_STRETCH, 0, 3); }
// mainboard_enable is executed as first thing after diff --git a/src/mainboard/getac/p470/mainboard.h b/src/mainboard/getac/p470/mainboard.h index 0e6b24c..d074960 100644 --- a/src/mainboard/getac/p470/mainboard.h +++ b/src/mainboard/getac/p470/mainboard.h @@ -13,6 +13,5 @@
struct acpi_rsdp;
-unsigned long mainboard_write_acpi_tables(struct device *device, - unsigned long start, +unsigned long mainboard_write_acpi_tables(struct device *device, unsigned long start, struct acpi_rsdp *rsdp); diff --git a/src/mainboard/getac/p470/mptable.c b/src/mainboard/getac/p470/mptable.c index c00102d..80c33df 100644 --- a/src/mainboard/getac/p470/mptable.c +++ b/src/mainboard/getac/p470/mptable.c @@ -41,28 +41,42 @@ mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0);
/* Builtin devices on Bus 0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x8, 0x2, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x7d, 0x2, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x2, 0x17); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x2, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x76, 0x2, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x77, 0x2, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x6c, 0x2, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x70, 0x2, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, 0x71, 0x2, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x8, 0x2, + 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x7d, 0x2, + 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x74, 0x2, + 0x17); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x75, 0x2, + 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x76, 0x2, + 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x77, 0x2, + 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x6c, 0x2, + 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x70, 0x2, + 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x71, 0x2, + 0x11);
/* Firewire 4:0.0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, 0x0, 0x2, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x4, 0x0, 0x2, + 0x10);
// riser slot top 5:8.0 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x20, 0x2, 0x14); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x5, 0x20, 0x2, + 0x14); // riser slot middle 5:9.0 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x24, 0x2, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x5, 0x24, 0x2, + 0x15); // riser slot bottom 5:a.0 - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, 0x28, 0x2, 0x16); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x5, 0x28, 0x2, + 0x16);
/* Onboard Ethernet */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x1, 0x0, 0x2, + 0x10);
/* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ mptable_lintsrc(mc, isa_bus); diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index 3f80664..a591307 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -36,18 +36,18 @@
printk(BIOS_SPEW, "\n Initializing drive bay...\n"); gpios = inl(DEFAULT_GPIOBASE + 0x38); // GPIO Level 2 - gpios |= (1 << 0); // GPIO33 = ODD - gpios |= (1 << 1); // GPIO34 = IDE_RST# - outl(gpios, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */ + gpios |= (1 << 0); // GPIO33 = ODD + gpios |= (1 << 1); // GPIO34 = IDE_RST# + outl(gpios, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */
gpios = inl(DEFAULT_GPIOBASE + 0x0c); // GPIO Level - gpios &= ~(1 << 13); // ?? - outl(gpios, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ + gpios &= ~(1 << 13); // ?? + outl(gpios, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
printk(BIOS_SPEW, "\n Initializing Ethernet NIC...\n"); gpios = inl(DEFAULT_GPIOBASE + 0x0c); // GPIO Level - gpios &= ~(1 << 24); // Enable LAN Power - outl(gpios, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ + gpios &= ~(1 << 24); // Enable LAN Power + outl(gpios, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ }
static void ich7_enable_lpc(void) @@ -61,9 +61,10 @@ // decode range pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0007); // decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN - | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN - | FDD_LPC_EN| lpt_en | COMB_LPC_EN | COMA_LPC_EN); + pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, + CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN + | GAMEL_LPC_EN | FDD_LPC_EN | lpt_en | COMB_LPC_EN + | COMA_LPC_EN); // Enable 0x02e0 - 0x2ff pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x001c02e1); // Enable 0x600 - 0x6ff @@ -93,7 +94,7 @@ { unsigned int port = dev >> 8; outb(reg, port); - outb(val, port+1); + outb(val, port + 1); }
static void early_superio_config(void) @@ -103,15 +104,15 @@ dev = PNP_DEV(0x4e, 0x00);
pnp_enter_ext_func_mode(dev); - pnp_write_register(dev, 0x02, 0x0e); // UART power - pnp_write_register(dev, 0x1b, (0x3e8 >> 2)); // UART3 base - pnp_write_register(dev, 0x1c, (0x2e8 >> 2)); // UART4 base + pnp_write_register(dev, 0x02, 0x0e); // UART power + pnp_write_register(dev, 0x1b, (0x3e8 >> 2)); // UART3 base + pnp_write_register(dev, 0x1c, (0x2e8 >> 2)); // UART4 base pnp_write_register(dev, 0x1d, (5 << 4) | 11); // UART3,4 IRQ - pnp_write_register(dev, 0x1e, 1); // no 32khz clock - pnp_write_register(dev, 0x24, (0x3f8 >> 2)); // UART1 base - pnp_write_register(dev, 0x28, (4 << 4) | 0); // UART1,2 IRQ - pnp_write_register(dev, 0x2c, 0); // DMA0 FIR - pnp_write_register(dev, 0x30, (0x600 >> 4)); // Runtime Register Block Base + pnp_write_register(dev, 0x1e, 1); // no 32khz clock + pnp_write_register(dev, 0x24, (0x3f8 >> 2)); // UART1 base + pnp_write_register(dev, 0x28, (4 << 4) | 0); // UART1,2 IRQ + pnp_write_register(dev, 0x2c, 0); // DMA0 FIR + pnp_write_register(dev, 0x30, (0x600 >> 4)); // Runtime Register Block Base
pnp_write_register(dev, 0x31, 0xce); // GPIO1 DIR pnp_write_register(dev, 0x32, 0x00); // GPIO1 POL @@ -144,8 +145,8 @@ static void rcba_config(void) { /* Set up virtual channel 0 */ - //RCBA32(0x0014) = 0x80000001; - //RCBA32(0x001c) = 0x03128010; + // RCBA32(0x0014) = 0x80000001; + // RCBA32(0x001c) = 0x03128010;
/* Device 1f interrupt pin register */ RCBA32(D31IP) = 0x00042220; diff --git a/src/mainboard/getac/p470/smihandler.c b/src/mainboard/getac/p470/smihandler.c index 5a82044..ca95447 100644 --- a/src/mainboard/getac/p470/smihandler.c +++ b/src/mainboard/getac/p470/smihandler.c @@ -115,7 +115,7 @@ case 0xde: printk(BIOS_DEBUG, "LAN power off\n"); reg32 = inl(DEFAULT_GPIOBASE + GP_LVL); - reg32 |= (1 << 24); // Disable LAN Power + reg32 |= (1 << 24); // Disable LAN Power outl(reg32, DEFAULT_GPIOBASE + GP_LVL); break; case 0xdf: @@ -151,27 +151,37 @@ u8 reg8;
switch (hotkey) { - case 0x3b: break; // Fn+F1 - case 0x3c: break; // Fn+F2 - case 0x3d: break; // Fn+F3 - case 0x3e: break; // Fn+F4 - case 0x3f: break; // Fn+F5 - case 0x40: // Fn+F6 (Decrease Display Brightness) - reg8 = ec_read(0x17); - reg8 = (reg8 > 8) ? (reg8 - 8) : 0; - ec_write(0x17, reg8); - return; - case 0x41: // Fn+F7 (Increase Display Brightness) - reg8 = ec_read(0x17); - reg8 += 8; - reg8 = (reg8 >= MAX_LCD_BRIGHTNESS) ? MAX_LCD_BRIGHTNESS : reg8; - ec_write(0x17, reg8); - return; - case 0x42: break; // Fn+F8 - case 0x43: break; // Fn+F9 - case 0x44: break; // Fn+F10 - case 0x57: break; // Fn+F11 - case 0x58: break; // Fn+F12 + case 0x3b: // Fn+F1 + break; + case 0x3c: // Fn+F2 + break; + case 0x3d: // Fn+F3 + break; + case 0x3e: // Fn+F4 + break; + case 0x3f: // Fn+F5 + break; + case 0x40: // Fn+F6 (Decrease Display Brightness) + reg8 = ec_read(0x17); + reg8 = (reg8 > 8) ? (reg8 - 8) : 0; + ec_write(0x17, reg8); + return; + case 0x41: // Fn+F7 (Increase Display Brightness) + reg8 = ec_read(0x17); + reg8 += 8; + reg8 = (reg8 >= MAX_LCD_BRIGHTNESS) ? MAX_LCD_BRIGHTNESS : reg8; + ec_write(0x17, reg8); + return; + case 0x42: // Fn+F8 + break; + case 0x43: // Fn+F9 + break; + case 0x44: // Fn+F10 + break; + case 0x57: // Fn+F11 + break; + case 0x58: // Fn+F12 + break; } printk(BIOS_DEBUG, "EC hotkey: %02x\n", hotkey); }
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31652 )
Change subject: getac/p470: Let clang-format handle the coding style ......................................................................
Patch Set 1:
(6 comments)
https://review.coreboot.org/#/c/31652/1/src/mainboard/getac/p470/cstates.c File src/mainboard/getac/p470/cstates.c:
https://review.coreboot.org/#/c/31652/1/src/mainboard/getac/p470/cstates.c@2... PS1, Line 23: {ACPI_ADDRESS_SPACE_FIXED, 1, 2, {1}, 0, 0}}, space required after that close brace '}'
https://review.coreboot.org/#/c/31652/1/src/mainboard/getac/p470/cstates.c@2... PS1, Line 28: {ACPI_ADDRESS_SPACE_IO, 8, 0, {0}, DEFAULT_PMBASE + LV2, 0}}, space required after that close brace '}'
https://review.coreboot.org/#/c/31652/1/src/mainboard/getac/p470/cstates.c@3... PS1, Line 33: {ACPI_ADDRESS_SPACE_IO, 8, 0, {0}, DEFAULT_PMBASE + LV3, 0}}, space required after that close brace '}'
https://review.coreboot.org/#/c/31652/1/src/mainboard/getac/p470/gpio.c File src/mainboard/getac/p470/gpio.c:
https://review.coreboot.org/#/c/31652/1/src/mainboard/getac/p470/gpio.c@103 PS1, Line 103: { that open brace { should be on the previous line
https://review.coreboot.org/#/c/31652/1/src/mainboard/getac/p470/gpio.c@111 PS1, Line 111: { that open brace { should be on the previous line
https://review.coreboot.org/#/c/31652/1/src/mainboard/getac/p470/irq_tables.... File src/mainboard/getac/p470/irq_tables.c:
https://review.coreboot.org/#/c/31652/1/src/mainboard/getac/p470/irq_tables.... PS1, Line 53: }}; space required after that close brace '}'
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31652 )
Change subject: getac/p470: Let clang-format handle the coding style ......................................................................
Patch Set 1:
Martin, what should we do about formatting disagreements between checkpatch and clang-format (like here)?
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31652 )
Change subject: getac/p470: Let clang-format handle the coding style ......................................................................
Patch Set 1:
Patch Set 1:
Martin, what should we do about formatting disagreements between checkpatch and clang-format (like here)?
We'll need to fix checkpatch.
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31652 )
Change subject: getac/p470: Let clang-format handle the coding style ......................................................................
Patch Set 1: Code-Review+2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31652 )
Change subject: getac/p470: Let clang-format handle the coding style ......................................................................
Patch Set 1:
(2 comments)
Patch Set 1:
Patch Set 1:
Martin, what should we do about formatting disagreements between checkpatch and clang-format (like here)?
We'll need to fix checkpatch.
I disagree. Both objections of checkpatch.pl make sense, and clang-format should follow them, if possible.
https://review.coreboot.org/#/c/31652/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/31652/1//COMMIT_MSG@10 PS1, Line 10: Could you please add the Clang version, you used for this?
https://review.coreboot.org/#/c/31652/1/src/mainboard/getac/p470/ec_oem.h File src/mainboard/getac/p470/ec_oem.h:
https://review.coreboot.org/#/c/31652/1/src/mainboard/getac/p470/ec_oem.h@24 PS1, Line 24: // 1: SMI event pending : #define EC_SMI_EVT (1 << 6) : : // 1: SCI event pending : #define EC_SCI_EVT (1 << 5) : : // controller is in burst mode : #define EC_BURST (1 << 4) : : // 1: byte in data register is command : // 0: byte in data register is data : #define EC_CMD (1 << 3) : : // 1: input buffer full (data ready for ec) : #define EC_IBF (1 << 1) : : // 1: output buffer full (data ready for host) : #define EC_OBF (1 << 0) : : /* EC_SC output */ : #define RD_EC 0x80 // Read Embedded Controller : #define WR_EC 0x81 // Write Embedded Controller : #define BE_EC 0x82 // Burst Enable Embedded Controller : #define BD_EC 0x83 // Burst Disable Embedded Controller : #define QR_EC 0x84 // Query Embedded Controller Both blocks should follow the same formatting style. Looks like a clang-format problem.
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31652 )
Change subject: getac/p470: Let clang-format handle the coding style ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/#/c/31652/1/src/mainboard/getac/p470/ec_oem.h File src/mainboard/getac/p470/ec_oem.h:
https://review.coreboot.org/#/c/31652/1/src/mainboard/getac/p470/ec_oem.h@24 PS1, Line 24: // 1: SMI event pending : #define EC_SMI_EVT (1 << 6) : : // 1: SCI event pending : #define EC_SCI_EVT (1 << 5) : : // controller is in burst mode : #define EC_BURST (1 << 4) : : // 1: byte in data register is command : // 0: byte in data register is data : #define EC_CMD (1 << 3) : : // 1: input buffer full (data ready for ec) : #define EC_IBF (1 << 1) : : // 1: output buffer full (data ready for host) : #define EC_OBF (1 << 0) : : /* EC_SC output */ : #define RD_EC 0x80 // Read Embedded Controller : #define WR_EC 0x81 // Write Embedded Controller : #define BE_EC 0x82 // Burst Enable Embedded Controller : #define BD_EC 0x83 // Burst Disable Embedded Controller : #define QR_EC 0x84 // Query Embedded Controller
Both blocks should follow the same formatting style. Looks like a clang-format problem.
I rearranged the EC_* entries manually because ad-hoc multiline comments and define blocks don't go well together. From clang-format's point of view the EC_* stuff is not a block but 6 individual defines.
Hello build bot (Jenkins), Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31652
to look at the new patch set (#2).
Change subject: getac/p470: Let clang-format handle the coding style ......................................................................
getac/p470: Let clang-format handle the coding style
Also make the format mandatory for the board.
Change-Id: Ib34af7c4db359e132b968fe8409580af05fba9e3 Signed-off-by: Patrick Georgi pgeorgi@google.com --- A .clang-format-scope M src/mainboard/getac/p470/acpi_tables.c M src/mainboard/getac/p470/cstates.c M src/mainboard/getac/p470/ec_oem.c M src/mainboard/getac/p470/ec_oem.h M src/mainboard/getac/p470/gpio.c M src/mainboard/getac/p470/hda_verb.c M src/mainboard/getac/p470/irq_tables.c M src/mainboard/getac/p470/mainboard.c M src/mainboard/getac/p470/mainboard.h M src/mainboard/getac/p470/mptable.c M src/mainboard/getac/p470/romstage.c M src/mainboard/getac/p470/smihandler.c 13 files changed, 179 insertions(+), 136 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/31652/2
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31652 )
Change subject: getac/p470: Let clang-format handle the coding style ......................................................................
Patch Set 2:
(6 comments)
https://review.coreboot.org/#/c/31652/2/src/mainboard/getac/p470/cstates.c File src/mainboard/getac/p470/cstates.c:
https://review.coreboot.org/#/c/31652/2/src/mainboard/getac/p470/cstates.c@2... PS2, Line 23: {ACPI_ADDRESS_SPACE_FIXED, 1, 2, 1, 0, 0}}, space required after that close brace '}'
https://review.coreboot.org/#/c/31652/2/src/mainboard/getac/p470/cstates.c@2... PS2, Line 28: {ACPI_ADDRESS_SPACE_IO, 8, 0, 0, DEFAULT_PMBASE + LV2, 0}}, space required after that close brace '}'
https://review.coreboot.org/#/c/31652/2/src/mainboard/getac/p470/cstates.c@3... PS2, Line 33: {ACPI_ADDRESS_SPACE_IO, 8, 0, 0, DEFAULT_PMBASE + LV3, 0}}, space required after that close brace '}'
https://review.coreboot.org/#/c/31652/2/src/mainboard/getac/p470/gpio.c File src/mainboard/getac/p470/gpio.c:
https://review.coreboot.org/#/c/31652/2/src/mainboard/getac/p470/gpio.c@103 PS2, Line 103: { that open brace { should be on the previous line
https://review.coreboot.org/#/c/31652/2/src/mainboard/getac/p470/gpio.c@111 PS2, Line 111: { that open brace { should be on the previous line
https://review.coreboot.org/#/c/31652/2/src/mainboard/getac/p470/irq_tables.... File src/mainboard/getac/p470/irq_tables.c:
https://review.coreboot.org/#/c/31652/2/src/mainboard/getac/p470/irq_tables.... PS2, Line 53: }}; space required after that close brace '}'
Patrick Georgi has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/31652 )
Change subject: getac/p470: Let clang-format handle the coding style ......................................................................
Abandoned
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31652 )
Change subject: getac/p470: Let clang-format handle the coding style ......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/getac/p470/ec_oem.h:
https://review.coreboot.org/c/coreboot/+/31652/comment/0e2114ab_4ef2004d PS1, Line 24: // 1: SMI event pending : #define EC_SMI_EVT (1 << 6) : : // 1: SCI event pending : #define EC_SCI_EVT (1 << 5) : : // controller is in burst mode : #define EC_BURST (1 << 4) : : // 1: byte in data register is command : // 0: byte in data register is data : #define EC_CMD (1 << 3) : : // 1: input buffer full (data ready for ec) : #define EC_IBF (1 << 1) : : // 1: output buffer full (data ready for host) : #define EC_OBF (1 << 0) : : /* EC_SC output */ : #define RD_EC 0x80 // Read Embedded Controller : #define WR_EC 0x81 // Write Embedded Controller : #define BE_EC 0x82 // Burst Enable Embedded Controller : #define BD_EC 0x83 // Burst Disable Embedded Controller : #define QR_EC 0x84 // Query Embedded Controller
I rearranged the EC_* entries manually because ad-hoc multiline comments and define blocks don't go […]
Thank you for the explanation. So, getting rid of the one multi-line comment would have also resulted in consistency?
// 1: byte in data register is command, 0: byte in data register is data
-
build bot (Jenkins) (Code Review) -
Martin Roth (Code Review)
-
Patrick Georgi (Code Review)
-
Paul Menzel (Code Review)