Change in coreboot[master]: src/soc/intel/*/include: Get list of devices that needs IRQ programming
Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34348 )
Change subject: src/soc/intel/*/include: Get list of devices that needs IRQ programming ......................................................................
src/soc/intel/*/include: Get list of devices that needs IRQ programming
This implementation adds SOC function that returns list of PCI devices that needs IRQ programming. This list can be further used to program IRQ for these devices.
Change-Id: I3482172f6cb549dece23e2b8b09b8b79578b83b7 Signed-off-by: Aamir Bohra aamir.bohra@intel.com --- M src/soc/intel/cannonlake/Makefile.inc A src/soc/intel/cannonlake/irq.c M src/soc/intel/icelake/Makefile.inc A src/soc/intel/icelake/irq.c 4 files changed, 150 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/34348/1
diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 8a4a8b7..ed0d09c 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -41,6 +41,7 @@ ramstage-y += graphics.c ramstage-y += gspi.c ramstage-y += i2c.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_ITSS_INTERRUPT_OVERRIDE) += irq.c ramstage-y += lockdown.c ramstage-y += lpc.c ramstage-y += me.c diff --git a/src/soc/intel/cannonlake/irq.c b/src/soc/intel/cannonlake/irq.c new file mode 100644 index 0000000..ce0e539 --- /dev/null +++ b/src/soc/intel/cannonlake/irq.c @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <intelblocks/irq.h> +#include <soc/pci_devs.h> +#include <stdint.h> + +static const int irq_devices[] = { + PCH_DEVFN_HDA, + PCH_DEVFN_SMBUS, + PCH_DEVFN_GBE, + PCH_DEVFN_TRACEHUB, + PCH_DEVFN_PCIE9, + PCH_DEVFN_PCIE10, + PCH_DEVFN_PCIE11, + PCH_DEVFN_PCIE12, + PCH_DEVFN_PCIE13, + PCH_DEVFN_PCIE14, + PCH_DEVFN_PCIE15, + PCH_DEVFN_PCIE16, + PCH_DEVFN_PCIE1, + PCH_DEVFN_PCIE2, + PCH_DEVFN_PCIE3, + PCH_DEVFN_PCIE4, + PCH_DEVFN_PCIE5, + PCH_DEVFN_PCIE6, + PCH_DEVFN_PCIE7, + PCH_DEVFN_PCIE8, + PCH_DEVFN_EMMC, + PCH_DEVFN_SATA, + PCH_DEVFN_CSE, + PCH_DEVFN_CSE_2, + PCH_DEVFN_CSE_IDER, + PCH_DEVFN_CSE_KT, + PCH_DEVFN_CSE_3, + PCH_DEVFN_CSE_4, + PCH_DEVFN_XHCI, + PCH_DEVFN_USBOTG, + PCH_DEVFN_CNViWIFI, + PCH_DEVFN_SDCARD, + PCH_DEVFN_ISH, + PCH_DEVFN_THERMAL, + PCH_DEVFN_UFS, + PCH_DEVFN_UART0, + PCH_DEVFN_UART1, + PCH_DEVFN_GSPI0, + PCH_DEVFN_GSPI1, + PCH_DEVFN_UART2, + PCH_DEVFN_I2C5, + PCH_DEVFN_I2C4, + PCH_DEVFN_I2C0, + PCH_DEVFN_I2C1, + PCH_DEVFN_I2C2, + PCH_DEVFN_I2C3, + PCH_DEVFN_GSPI2, +}; + +const int *get_soc_irq_devices(size_t *size) +{ + *size = ARRAY_SIZE(irq_devices); + return irq_devices; +} diff --git a/src/soc/intel/icelake/Makefile.inc b/src/soc/intel/icelake/Makefile.inc index cd02934..2973e15 100644 --- a/src/soc/intel/icelake/Makefile.inc +++ b/src/soc/intel/icelake/Makefile.inc @@ -43,6 +43,7 @@ ramstage-y += graphics.c ramstage-y += gspi.c ramstage-y += i2c.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_ITSS_INTERRUPT_OVERRIDE) += irq.c ramstage-y += lockdown.c ramstage-y += memmap.c ramstage-y += p2sb.c diff --git a/src/soc/intel/icelake/irq.c b/src/soc/intel/icelake/irq.c new file mode 100644 index 0000000..ce0e539 --- /dev/null +++ b/src/soc/intel/icelake/irq.c @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <intelblocks/irq.h> +#include <soc/pci_devs.h> +#include <stdint.h> + +static const int irq_devices[] = { + PCH_DEVFN_HDA, + PCH_DEVFN_SMBUS, + PCH_DEVFN_GBE, + PCH_DEVFN_TRACEHUB, + PCH_DEVFN_PCIE9, + PCH_DEVFN_PCIE10, + PCH_DEVFN_PCIE11, + PCH_DEVFN_PCIE12, + PCH_DEVFN_PCIE13, + PCH_DEVFN_PCIE14, + PCH_DEVFN_PCIE15, + PCH_DEVFN_PCIE16, + PCH_DEVFN_PCIE1, + PCH_DEVFN_PCIE2, + PCH_DEVFN_PCIE3, + PCH_DEVFN_PCIE4, + PCH_DEVFN_PCIE5, + PCH_DEVFN_PCIE6, + PCH_DEVFN_PCIE7, + PCH_DEVFN_PCIE8, + PCH_DEVFN_EMMC, + PCH_DEVFN_SATA, + PCH_DEVFN_CSE, + PCH_DEVFN_CSE_2, + PCH_DEVFN_CSE_IDER, + PCH_DEVFN_CSE_KT, + PCH_DEVFN_CSE_3, + PCH_DEVFN_CSE_4, + PCH_DEVFN_XHCI, + PCH_DEVFN_USBOTG, + PCH_DEVFN_CNViWIFI, + PCH_DEVFN_SDCARD, + PCH_DEVFN_ISH, + PCH_DEVFN_THERMAL, + PCH_DEVFN_UFS, + PCH_DEVFN_UART0, + PCH_DEVFN_UART1, + PCH_DEVFN_GSPI0, + PCH_DEVFN_GSPI1, + PCH_DEVFN_UART2, + PCH_DEVFN_I2C5, + PCH_DEVFN_I2C4, + PCH_DEVFN_I2C0, + PCH_DEVFN_I2C1, + PCH_DEVFN_I2C2, + PCH_DEVFN_I2C3, + PCH_DEVFN_GSPI2, +}; + +const int *get_soc_irq_devices(size_t *size) +{ + *size = ARRAY_SIZE(irq_devices); + return irq_devices; +}
Hello Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34348
to look at the new patch set (#7).
Change subject: soc/intel/{cnl,icl}: Get list of PCI devices that needs IRQ programming ......................................................................
soc/intel/{cnl,icl}: Get list of PCI devices that needs IRQ programming
This implementation adds SOC function that returns list of PCI devices that needs IRQ programming. This list can be further used to program IRQ for these devices.
Change-Id: I3482172f6cb549dece23e2b8b09b8b79578b83b7 Signed-off-by: Aamir Bohra aamir.bohra@intel.com --- M src/soc/intel/cannonlake/Makefile.inc A src/soc/intel/cannonlake/irq.c M src/soc/intel/icelake/Makefile.inc A src/soc/intel/icelake/irq.c 4 files changed, 150 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/34348/7
Hello Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34348
to look at the new patch set (#9).
Change subject: soc/intel/{cnl,icl}: Get list of PCI devices that needs IRQ programming ......................................................................
soc/intel/{cnl,icl}: Get list of PCI devices that needs IRQ programming
This implementation adds SOC function that returns list of PCI devices that needs IRQ programming. This list can be further used to program IRQ for these devices.
Change-Id: I3482172f6cb549dece23e2b8b09b8b79578b83b7 Signed-off-by: Aamir Bohra aamir.bohra@intel.com --- M src/soc/intel/cannonlake/Makefile.inc A src/soc/intel/cannonlake/irq.c M src/soc/intel/icelake/Makefile.inc A src/soc/intel/icelake/irq.c 4 files changed, 150 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/34348/9
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34348 )
Change subject: soc/intel/{cnl,icl}: Get list of PCI devices that needs IRQ programming ......................................................................
Patch Set 12: Code-Review+1
Hello Patrick Rudolph, Tim Wawrzynczak, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34348
to look at the new patch set (#13).
Change subject: soc/intel/{cnl,icl}: Get list of PCI devices that needs IRQ programming ......................................................................
soc/intel/{cnl,icl}: Get list of PCI devices that needs IRQ programming
This implementation adds SOC function that returns list of PCI devices that needs IRQ programming. This list can be further used to program IRQ for these devices.
Change-Id: I3482172f6cb549dece23e2b8b09b8b79578b83b7 Signed-off-by: Aamir Bohra aamir.bohra@intel.com --- M src/soc/intel/cannonlake/Makefile.inc A src/soc/intel/cannonlake/irq.c M src/soc/intel/icelake/Makefile.inc A src/soc/intel/icelake/irq.c 4 files changed, 151 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/34348/13
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34348 )
Change subject: soc/intel/{cnl,icl}: Get list of PCI devices that needs IRQ programming ......................................................................
Patch Set 13: Code-Review+1
Good eye on the pci_devfn_t
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34348 )
Change subject: soc/intel/{cnl,icl}: Get list of PCI devices that needs IRQ programming ......................................................................
Patch Set 13: Code-Review+2
Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34348 )
Change subject: soc/intel/{cnl,icl}: Get list of PCI devices that needs IRQ programming ......................................................................
Patch Set 15: Code-Review+1
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34348 )
Change subject: soc/intel/{cnl,icl}: Get list of PCI devices that needs IRQ programming ......................................................................
Patch Set 15:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34348/15/src/soc/intel/icelake/irq.... File src/soc/intel/icelake/irq.c:
https://review.coreboot.org/c/coreboot/+/34348/15/src/soc/intel/icelake/irq.... PS15, Line 20: static const pci_devfn_t irq_devices[] = { are there any devices that are in this list but not in the (dynamic) devicetree or vice-versa?
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34348 )
Change subject: soc/intel/{cnl,icl}: Get list of PCI devices that needs IRQ programming ......................................................................
Patch Set 15:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34348/15/src/soc/intel/icelake/irq.... File src/soc/intel/icelake/irq.c:
https://review.coreboot.org/c/coreboot/+/34348/15/src/soc/intel/icelake/irq.... PS15, Line 20: static const pci_devfn_t irq_devices[] = {
are there any devices that are in this list but not in the (dynamic) devicetree or vice-versa?
Yes, Host bridge, integrated graphics, PMC, p2SB
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34348 )
Change subject: soc/intel/{cnl,icl}: Get list of PCI devices that needs IRQ programming ......................................................................
Patch Set 16:
This change is ready for review.
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Aamir Bohra (Code Review) -
Lean Sheng Tan (Code Review)
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Patrick Georgi (Code Review)
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Tim Wawrzynczak (Code Review)