Change in ...coreboot[master]: mb/google/sarien/variants/sarien: Update GPIO H3 for DVT1
John Su has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31412
Change subject: mb/google/sarien/variants/sarien: Update GPIO H3 for DVT1 ......................................................................
mb/google/sarien/variants/sarien: Update GPIO H3 for DVT1
Follow b:123461432#5 to updte GPIO H3(CNVI_EN#) for DVT1. Update setting GPIO H3 to output and low level.
BUG=b:123461432 TEST=Built and tested on sarien system
Change-Id: I6a56df9a7bf75f49133a646312ae5093c2652698 Signed-off-by: John Su john_su@compal.corp-partner.google.com --- M src/mainboard/google/sarien/variants/sarien/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/31412/1
diff --git a/src/mainboard/google/sarien/variants/sarien/gpio.c b/src/mainboard/google/sarien/variants/sarien/gpio.c index e735fee..ff311b1 100644 --- a/src/mainboard/google/sarien/variants/sarien/gpio.c +++ b/src/mainboard/google/sarien/variants/sarien/gpio.c @@ -188,7 +188,7 @@ /* I2S2_SCLK */ PAD_NC(GPP_H0, NONE), /* I2S2_SFRM */ PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3), /* CNV_RF_RESET# */ /* I2S2_TXD */ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), /* CLKREQ_CNV# */ -/* I2S2_RXD */ PAD_CFG_GPI(GPP_H3, NONE, DEEP), /* CNVI_EN# */ +/* I2S2_RXD */ PAD_CFG_GPO(GPP_H3, 0, DEEP), /* CNVI_EN# */ /* I2C2_SDA */ PAD_NC(GPP_H4, NONE), /* T388 */ /* I2C2_SCL */ PAD_NC(GPP_H5, NONE), /* T389 */ /* I2C3_SDA */ PAD_NC(GPP_H6, NONE), /* T378 */
Hello Duncan Laurie, Lijian Zhao, Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31412
to look at the new patch set (#2).
Change subject: mb/google/sarien/variants/sarien: Update GPIO H3 for DVT1 ......................................................................
mb/google/sarien/variants/sarien: Update GPIO H3 for DVT1
Follow b:123461432#5 to update GPIO H3(CNVI_EN#) for DVT1. Update setting GPIO H3 to output and low level.
BUG=b:123461432 TEST=Built and tested on sarien system
Change-Id: I6a56df9a7bf75f49133a646312ae5093c2652698 Signed-off-by: John Su john_su@compal.corp-partner.google.com --- M src/mainboard/google/sarien/variants/sarien/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/31412/2
Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31412 )
Change subject: mb/google/sarien/variants/sarien: Update GPIO H3 for DVT1 ......................................................................
Patch Set 2: Code-Review+2
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31412 )
Change subject: mb/google/sarien/variants/sarien: Update GPIO H3 for DVT1 ......................................................................
mb/google/sarien/variants/sarien: Update GPIO H3 for DVT1
Follow b:123461432#5 to update GPIO H3(CNVI_EN#) for DVT1. Update setting GPIO H3 to output and low level.
BUG=b:123461432 TEST=Built and tested on sarien system
Change-Id: I6a56df9a7bf75f49133a646312ae5093c2652698 Signed-off-by: John Su john_su@compal.corp-partner.google.com Reviewed-on: https://review.coreboot.org/c/31412 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Duncan Laurie dlaurie@chromium.org --- M src/mainboard/google/sarien/variants/sarien/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Duncan Laurie: Looks good to me, approved
diff --git a/src/mainboard/google/sarien/variants/sarien/gpio.c b/src/mainboard/google/sarien/variants/sarien/gpio.c index e735fee..ff311b1 100644 --- a/src/mainboard/google/sarien/variants/sarien/gpio.c +++ b/src/mainboard/google/sarien/variants/sarien/gpio.c @@ -188,7 +188,7 @@ /* I2S2_SCLK */ PAD_NC(GPP_H0, NONE), /* I2S2_SFRM */ PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3), /* CNV_RF_RESET# */ /* I2S2_TXD */ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), /* CLKREQ_CNV# */ -/* I2S2_RXD */ PAD_CFG_GPI(GPP_H3, NONE, DEEP), /* CNVI_EN# */ +/* I2S2_RXD */ PAD_CFG_GPO(GPP_H3, 0, DEEP), /* CNVI_EN# */ /* I2C2_SDA */ PAD_NC(GPP_H4, NONE), /* T388 */ /* I2C2_SCL */ PAD_NC(GPP_H5, NONE), /* T389 */ /* I2C3_SDA */ PAD_NC(GPP_H6, NONE), /* T378 */
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Duncan Laurie (Code Review) -
John Su (Code Review)
-
Patrick Georgi (Code Review)