New patch to review for coreboot: bb6c350 southbridge/intel/i82801ix: Remove a trailing whitespace
HAOUAS Elyes (ehaouas@noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6339
-gerrit
commit bb6c3500fcaea8564df93c2c6c70464fd852fca4 Author: Elyes HAOUAS ehaouas@noos.fr Date: Tue Jul 22 19:49:26 2014 +0200
southbridge/intel/i82801ix: Remove a trailing whitespace
Change-Id: Ia4d5ec28764da74200e7643a6e9f245b9712e8d7 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- src/southbridge/intel/i82801ix/i82801ix.h | 22 +++++++++++----------- src/southbridge/intel/i82801ix/smi.c | 10 +++++----- 2 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h index d84af3a..7fd71be 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.h +++ b/src/southbridge/intel/i82801ix/i82801ix.h @@ -46,13 +46,13 @@ #define APM_CNT 0xb2
#define PM1_STS 0x00 -#define PWRBTN_STS (1 << 8) -#define RTC_STS (1 << 10) +#define PWRBTN_STS (1 << 8) +#define RTC_STS (1 << 10) #define PM1_EN 0x02 -#define PWRBTN_EN (1 << 8) -#define GBL_EN (1 << 5) +#define PWRBTN_EN (1 << 8) +#define GBL_EN (1 << 5) #define PM1_CNT 0x04 -#define SCI_EN (1 << 0) +#define SCI_EN (1 << 0) #define PM_LV2 0x14 #define PM_LV3 0x15 #define PM_LV4 0x16 @@ -60,12 +60,12 @@ #define PM_LV6 0x18 #define GPE0_STS 0x20 #define SMI_EN 0x30 -#define PERIODIC_EN (1 << 14) -#define TCO_EN (1 << 13) -#define APMC_EN (1 << 5) -#define BIOS_EN (1 << 2) -#define EOS (1 << 1) -#define GBL_SMI_EN (1 << 0) +#define PERIODIC_EN (1 << 14) +#define TCO_EN (1 << 13) +#define APMC_EN (1 << 5) +#define BIOS_EN (1 << 2) +#define EOS (1 << 1) +#define GBL_SMI_EN (1 << 0) #define SMI_STS 0x34 #define ALT_GP_SMI_EN 0x38 #define ALT_GP_SMI_STS 0x3a diff --git a/src/southbridge/intel/i82801ix/smi.c b/src/southbridge/intel/i82801ix/smi.c index de9931c..3b4ba1c 100644 --- a/src/southbridge/intel/i82801ix/smi.c +++ b/src/southbridge/intel/i82801ix/smi.c @@ -36,11 +36,11 @@ extern unsigned char _binary_smm_size;
/* I945/GM45 */ #define SMRAM 0x9d -#define D_OPEN (1 << 6) -#define D_CLS (1 << 5) -#define D_LCK (1 << 4) -#define G_SMRAME (1 << 3) -#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) +#define D_OPEN (1 << 6) +#define D_CLS (1 << 5) +#define D_LCK (1 << 4) +#define G_SMRAME (1 << 3) +#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
/* While we read PMBASE dynamically in case it changed, let's * initialize it with a sane value
-
HAOUAS Elyes