[XS] Change in coreboot[main]: soc/alderlake/romstage: Set UsbTcPortEnPreMem UPD based on devicetree

[Felix Singer (Code Review)]

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80500?usp=email )

Change subject: soc/alderlake/romstage: Set UsbTcPortEnPreMem UPD based on devicetree
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soc/alderlake/romstage: Set UsbTcPortEnPreMem UPD based on devicetree

The UsbTcPortEn UPD for FSP-S is being set in ramstage, however the
equivalent FSP-M UPD, the UsbTcPortEnPreMem, was not being set.
Following the Meteor Lake example, set the UsbTcPortEnPreMem UPD
as well for Alder Lake.

Setting this FSP-M UPD will cause FSP to properly program sideband
use BSSB_LSx pins for the enabled Type-C ports. Required for proper
DCI debug and TCSS initialization flow.

Change-Id: If3b79167ec1769ddfb7d28a6c78a3e80bd10afe7
Signed-off-by: Michał Żygowski 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80500
Reviewed-by: Nico Huber 
Tested-by: build bot (Jenkins) 
Reviewed-by: Felix Singer 
---
M src/soc/intel/alderlake/romstage/fsp_params.c
1 file changed, 5 insertions(+), 0 deletions(-)

Approvals:
  Felix Singer: Looks good to me, approved
  Nico Huber: Looks good to me, but someone else must approve
  build bot (Jenkins): Verified

diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index 84f83e3..d917e6c 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -271,6 +271,11 @@
    m_cfg->TcssDma0En = is_devfn_enabled(SA_DEVFN_TCSS_DMA0);
    m_cfg->TcssDma1En = is_devfn_enabled(SA_DEVFN_TCSS_DMA1);

+	m_cfg->UsbTcPortEnPreMem = 0;
+	for (int i = 0; i < MAX_TYPE_C_PORTS; i++)
+		if (config->tcss_ports[i].enable)
+			m_cfg->UsbTcPortEnPreMem |= BIT(i);
+
 #if (CONFIG(SOC_INTEL_RAPTORLAKE) && !CONFIG(FSP_USE_REPO)) || \
    (!CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) && CONFIG(FSP_USE_REPO))
    m_cfg->DisableDynamicTccoldHandshake =