[S] Change in coreboot[main]: soc/amd/common/block: Read SPI rom remapping

[Patrick Rudolph (Code Review)]

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier.

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87175?usp=email )

Change subject: soc/amd/common/block: Read SPI rom remapping
......................................................................

soc/amd/common/block: Read SPI rom remapping

When a SPI ROM greater than 16MByte is being used it will be split
into 16MByte chunks that can be remapped in HW as an automatic recovery
mechanism. As an example when the EFS in the first 16MByte is corrupted
and the second 16MByte EFS is valid the HW will switch pages. The automatic
address translation of the MMIO ROM needs to be accounted when accessing
the ROM2/ROM3 BAR.

Add a function to retrieve the current address remapping and print it in
show_spi_speeds_and_modes() for debugging purposes.

Document 56780

Change-Id: I046e029e6135ab57f79b675c62b233203f00d705
Signed-off-by: Patrick Rudolph 
---
M src/soc/amd/common/block/include/amdblocks/spi.h
M src/soc/amd/common/block/spi/fch_spi.c
2 files changed, 18 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/87175/1

diff --git a/src/soc/amd/common/block/include/amdblocks/spi.h b/src/soc/amd/common/block/include/amdblocks/spi.h
index eafc2c2..4fefc2f 100644
--- a/src/soc/amd/common/block/include/amdblocks/spi.h
+++ b/src/soc/amd/common/block/include/amdblocks/spi.h
@@ -71,6 +71,7 @@
 #define   SPI_RD4DW_EN_HOST		BIT(15)

#define SPI_ROM_PAGE			0x5c
+#define   SPI_ROM_PAGE_SEL		(BIT(0) | BIT(1))

#define SPI_FIFO			0x80
 #define SPI_FIFO_LAST_BYTE		0xc6 /* 0xc7 for Cezanne */
@@ -124,6 +125,9 @@
 void spi_write16(uint8_t reg, uint16_t val);
 void spi_write32(uint8_t reg, uint32_t val);

+/* Returns the active SPI ROM remapping */
+uint8_t fch_spi_rom_remapping(void);
+
 void fch_spi_config_modes(void);
 void mainboard_spi_cfg_override(uint8_t *fast_speed, uint8_t *read_mode);

diff --git a/src/soc/amd/common/block/spi/fch_spi.c b/src/soc/amd/common/block/spi/fch_spi.c
index d9708b1..fc182fc 100644
--- a/src/soc/amd/common/block/spi/fch_spi.c
+++ b/src/soc/amd/common/block/spi/fch_spi.c
@@ -32,10 +32,18 @@
    "Fast Read"
 };

+static const char *remapping[8] = {
+	"0-1-2-3",
+	"1-0-3-2",
+	"2-3-0-1",
+	"3-2-1-0",
+};
+
 void show_spi_speeds_and_modes(void)
 {
    uint16_t val16 = spi_read16(SPI100_SPEED_CONFIG);
    uint32_t val32 = spi_read32(SPI_CNTRL0);
+	uint8_t val8 = fch_spi_rom_remapping();

printk(BIOS_DEBUG, "SPI normal read speed: %s\n",
           spi_speed_str[DECODE_SPI_NORMAL_SPEED(val16)]);
@@ -48,6 +56,7 @@
    printk(BIOS_DEBUG, "SPI100: %s\n",
           spi_read16(SPI100_ENABLE) & SPI_USE_SPI100 ? "Enabled" : "Disabled");
    printk(BIOS_DEBUG, "SPI Read Mode: %s\n", read_mode_str[DECODE_SPI_READ_MODE(val32)]);
+	printk(BIOS_DEBUG, "SPI ROM mapping: %s\n", remapping[val8]);
 }

void __weak mainboard_spi_cfg_override(uint8_t *fast_speed, uint8_t *read_mode)
@@ -96,6 +105,11 @@
    spi_write32(SPI_CNTRL0, val | SPI_READ_MODE(mode));
 }

+uint8_t fch_spi_rom_remapping(void)
+{
+	return spi_read8(SPI_ROM_PAGE) & SPI_ROM_PAGE_SEL;
+}
+
 void fch_spi_config_modes(void)
 {
    uint8_t read_mode, fast_speed;