EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48793 )
Change subject: soc/intel/alderlake: Update chipset.cb for TSCC and USB ......................................................................
soc/intel/alderlake: Update chipset.cb for TSCC and USB
Refer TGL to add alias for TCSS and USB ports.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I803dad0af09b26a55ffb767826ba79cf61de04ca --- M src/soc/intel/alderlake/chipset.cb 1 file changed, 92 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/48793/1
diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb index de880e3..ed6d424 100644 --- a/src/soc/intel/alderlake/chipset.cb +++ b/src/soc/intel/alderlake/chipset.cb @@ -6,14 +6,52 @@ device pci 04.0 alias dtt off end device pci 06.0 alias pcie4_0 off end device pci 06.2 alias pcie4_1 off end - device pci 07.0 alias tbt_pcie_rp0 off end - device pci 07.1 alias tbt_pcie_rp1 off end - device pci 07.2 alias tbt_pcie_rp2 off end - device pci 07.3 alias tbt_pcie_rp3 off end + device pci 07.0 alias tbt_pcie_rp0 off + chip soc/intel/common/block/usb4 + use tbt_dma0 as usb4_port + device generic 0 on end + end + end + device pci 07.1 alias tbt_pcie_rp1 off + chip soc/intel/common/block/usb4 + use tbt_dma0 as usb4_port + device generic 1 on end + end + end + device pci 07.2 alias tbt_pcie_rp2 off + chip soc/intel/common/block/usb4 + use tbt_dma1 as usb4_port + device generic 0 on end + end + end + device pci 07.3 alias tbt_pcie_rp3 off + chip soc/intel/common/block/usb4 + use tbt_dma1 as usb4_port + device generic 1 on end + end + end device pci 08.0 alias gna off end device pci 09.0 alias north_tracehub off end device pci 0a.0 alias crashlog off end - device pci 0d.0 alias tcss_xhci off end + device pci 0d.0 alias tcss_xhci off + chip drivers/usb/acpi + register "type" = "UPC_TYPE_HUB" + device usb 0.0 alias tcss_root_hub off + chip drivers/usb/acpi + device usb 3.0 alias tcss_usb3_port1 off end + end + chip drivers/usb/acpi + device usb 3.1 alias tcss_usb3_port2 off end + end + chip drivers/usb/acpi + device usb 3.2 alias tcss_usb3_port3 off end + end + chip drivers/usb/acpi + device usb 3.3 alias tcss_usb3_port4 off end + end + end + end + end device pci 0d.1 alias tcss_xdci off end device pci 0d.2 alias tcss_dma0 off end device pci 0d.3 alias tcss_dma1 off end @@ -24,7 +62,55 @@ device pci 12.0 alias ish off end device pci 12.6 alias gspi2 off end device pci 13.0 alias gspi3 off end - device pci 14.0 alias xhci off end + device pci 14.0 alias xhci off + chip drivers/usb/acpi + register "type" = "UPC_TYPE_HUB" + device usb 0.0 alias xhci_root_hub off + chip drivers/usb/acpi + device usb 2.0 alias usb2_port1 off end + end + chip drivers/usb/acpi + device usb 2.1 alias usb2_port2 off end + end + chip drivers/usb/acpi + device usb 2.2 alias usb2_port3 off end + end + chip drivers/usb/acpi + device usb 2.3 alias usb2_port4 off end + end + chip drivers/usb/acpi + device usb 2.4 alias usb2_port5 off end + end + chip drivers/usb/acpi + device usb 2.5 alias usb2_port6 off end + end + chip drivers/usb/acpi + device usb 2.6 alias usb2_port7 off end + end + chip drivers/usb/acpi + device usb 2.7 alias usb2_port8 off end + end + chip drivers/usb/acpi + device usb 2.8 alias usb2_port9 off end + end + chip drivers/usb/acpi + device usb 2.9 alias usb2_port10 off end + end + chip drivers/usb/acpi + device usb 3.0 alias usb3_port1 off end + end + chip drivers/usb/acpi + device usb 3.1 alias usb3_port2 off end + end + chip drivers/usb/acpi + device usb 3.2 alias usb3_port3 off end + end + chip drivers/usb/acpi + device usb 3.3 alias usb3_port4 off end + end + end + end + end device pci 14.1 alias usb_otg off end device pci 14.2 alias shared_sram off end device pci 14.3 alias cnvi_wifi off end
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48793 )
Change subject: soc/intel/alderlake: Update chipset.cb for TSCC and USB ......................................................................
Patch Set 1:
We can reuse this as well.
Hello build bot (Jenkins), Tim Wawrzynczak, Subrata Banik, Aamir Bohra, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48793
to look at the new patch set (#2).
Change subject: soc/intel/alderlake: Update chipset.cb for TSCC and USB ......................................................................
soc/intel/alderlake: Update chipset.cb for TSCC and USB
Refer TGL to add alias for TCSS and USB ports.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I803dad0af09b26a55ffb767826ba79cf61de04ca --- M src/soc/intel/alderlake/chipset.cb 1 file changed, 92 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/48793/2
Hello build bot (Jenkins), Tim Wawrzynczak, Subrata Banik, Aamir Bohra, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48793
to look at the new patch set (#3).
Change subject: soc/intel/alderlake: Update chipset.cb for TSCC and USB ......................................................................
soc/intel/alderlake: Update chipset.cb for TSCC and USB
Refer TGL to add alias for TCSS and USB ports.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I803dad0af09b26a55ffb767826ba79cf61de04ca --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/chipset.cb 2 files changed, 96 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/48793/3
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48793 )
Change subject: soc/intel/alderlake: Update chipset.cb for TSCC and USB ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/48793/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/48793/3//COMMIT_MSG@7 PS3, Line 7: TSCC Sorry, where is this in the diff?
https://review.coreboot.org/c/coreboot/+/48793/3//COMMIT_MSG@9 PS3, Line 9: Refer TGL to add alias for TCSS and USB ports. I do not understand this phrase.
Hello build bot (Jenkins), Tim Wawrzynczak, Subrata Banik, Aamir Bohra, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48793
to look at the new patch set (#4).
Change subject: soc/intel/alderlake: Update chipset.cb for TCSS and USB ......................................................................
soc/intel/alderlake: Update chipset.cb for TCSS and USB
Follow TGL chipset.cb to add alias for TCSS and USB ports.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I803dad0af09b26a55ffb767826ba79cf61de04ca --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/chipset.cb 2 files changed, 96 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/48793/4
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48793 )
Change subject: soc/intel/alderlake: Update chipset.cb for TCSS and USB ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/48793/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/48793/3//COMMIT_MSG@7 PS3, Line 7: TSCC
Sorry, where is this in the diff?
Done
https://review.coreboot.org/c/coreboot/+/48793/3//COMMIT_MSG@9 PS3, Line 9: Refer TGL to add alias for TCSS and USB ports.
I do not understand this phrase.
Done
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48793 )
Change subject: soc/intel/alderlake: Update chipset.cb for TCSS and USB ......................................................................
Patch Set 4: Code-Review+2
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48793 )
Change subject: soc/intel/alderlake: Update chipset.cb for TCSS and USB ......................................................................
Patch Set 5:
Please help submit this...
Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48793 )
Change subject: soc/intel/alderlake: Update chipset.cb for TCSS and USB ......................................................................
soc/intel/alderlake: Update chipset.cb for TCSS and USB
Follow TGL chipset.cb to add alias for TCSS and USB ports.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I803dad0af09b26a55ffb767826ba79cf61de04ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/48793 Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/chipset.cb 2 files changed, 96 insertions(+), 6 deletions(-)
Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index a77acc3..c73df50 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -14,6 +14,7 @@ select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_SUPPORTS_PM_TIMER_EMULATION + select DRIVERS_USB_ACPI select FSP_COMPRESS_FSP_S_LZ4 select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW select FSP_M_XIP @@ -52,6 +53,9 @@ select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP + select SOC_INTEL_COMMON_BLOCK_USB4 + select SOC_INTEL_COMMON_BLOCK_USB4_PCIE + select SOC_INTEL_COMMON_BLOCK_USB4_XHCI select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb index de880e3..de97a57 100644 --- a/src/soc/intel/alderlake/chipset.cb +++ b/src/soc/intel/alderlake/chipset.cb @@ -6,14 +6,52 @@ device pci 04.0 alias dtt off end device pci 06.0 alias pcie4_0 off end device pci 06.2 alias pcie4_1 off end - device pci 07.0 alias tbt_pcie_rp0 off end - device pci 07.1 alias tbt_pcie_rp1 off end - device pci 07.2 alias tbt_pcie_rp2 off end - device pci 07.3 alias tbt_pcie_rp3 off end + device pci 07.0 alias tbt_pcie_rp0 off + chip soc/intel/common/block/usb4 + use tcss_dma0 as usb4_port + device generic 0 on end + end + end + device pci 07.1 alias tbt_pcie_rp1 off + chip soc/intel/common/block/usb4 + use tcss_dma0 as usb4_port + device generic 1 on end + end + end + device pci 07.2 alias tbt_pcie_rp2 off + chip soc/intel/common/block/usb4 + use tcss_dma1 as usb4_port + device generic 0 on end + end + end + device pci 07.3 alias tbt_pcie_rp3 off + chip soc/intel/common/block/usb4 + use tcss_dma1 as usb4_port + device generic 1 on end + end + end device pci 08.0 alias gna off end device pci 09.0 alias north_tracehub off end device pci 0a.0 alias crashlog off end - device pci 0d.0 alias tcss_xhci off end + device pci 0d.0 alias tcss_xhci off + chip drivers/usb/acpi + register "type" = "UPC_TYPE_HUB" + device usb 0.0 alias tcss_root_hub off + chip drivers/usb/acpi + device usb 3.0 alias tcss_usb3_port1 off end + end + chip drivers/usb/acpi + device usb 3.1 alias tcss_usb3_port2 off end + end + chip drivers/usb/acpi + device usb 3.2 alias tcss_usb3_port3 off end + end + chip drivers/usb/acpi + device usb 3.3 alias tcss_usb3_port4 off end + end + end + end + end device pci 0d.1 alias tcss_xdci off end device pci 0d.2 alias tcss_dma0 off end device pci 0d.3 alias tcss_dma1 off end @@ -24,7 +62,55 @@ device pci 12.0 alias ish off end device pci 12.6 alias gspi2 off end device pci 13.0 alias gspi3 off end - device pci 14.0 alias xhci off end + device pci 14.0 alias xhci off + chip drivers/usb/acpi + register "type" = "UPC_TYPE_HUB" + device usb 0.0 alias xhci_root_hub off + chip drivers/usb/acpi + device usb 2.0 alias usb2_port1 off end + end + chip drivers/usb/acpi + device usb 2.1 alias usb2_port2 off end + end + chip drivers/usb/acpi + device usb 2.2 alias usb2_port3 off end + end + chip drivers/usb/acpi + device usb 2.3 alias usb2_port4 off end + end + chip drivers/usb/acpi + device usb 2.4 alias usb2_port5 off end + end + chip drivers/usb/acpi + device usb 2.5 alias usb2_port6 off end + end + chip drivers/usb/acpi + device usb 2.6 alias usb2_port7 off end + end + chip drivers/usb/acpi + device usb 2.7 alias usb2_port8 off end + end + chip drivers/usb/acpi + device usb 2.8 alias usb2_port9 off end + end + chip drivers/usb/acpi + device usb 2.9 alias usb2_port10 off end + end + chip drivers/usb/acpi + device usb 3.0 alias usb3_port1 off end + end + chip drivers/usb/acpi + device usb 3.1 alias usb3_port2 off end + end + chip drivers/usb/acpi + device usb 3.2 alias usb3_port3 off end + end + chip drivers/usb/acpi + device usb 3.3 alias usb3_port4 off end + end + end + end + end device pci 14.1 alias usb_otg off end device pci 14.2 alias shared_sram off end device pci 14.3 alias cnvi_wifi off end
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EricR Lai (Code Review) -
Paul Menzel (Code Review)
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Tim Wawrzynczak (Code Review)