[S] Change in coreboot[main]: soc/intel/meteorlake: Update TBT PCIe Reg Map offsets for QS

[Ravishankar Sarawadi (Code Review)]

Attention is currently required from: Cliff Huang, Eran Mitrani, Eric Lai, Jakub Czapiga, Jamie Ryu, Kapil Porwal, Subrata Banik, Tarun, Utkarsh H Patel.

Ravishankar Sarawadi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78163?usp=email )

Change subject: soc/intel/meteorlake: Update TBT PCIe Reg Map offsets for QS
......................................................................

Patch Set 6:

(2 comments)

Patchset:

PS6:
> which doc should follow to reflect this change ? […]

This change is not part of any doc, but I will let you if could get some reference.
Yes this is to do with new revisions coming in with Prod SOC.

File src/soc/intel/meteorlake/acpi/tcss_pcierp.asl:

https://review.coreboot.org/c/coreboot/+/78163/comment/92b8d4b8_20aced3c :
PS6, Line 3: 0xC00
> shouldn't you make this value also configurable based on Config selection ? i.e. […]

0xC00 is size increase to access higher offsets so IMO no need to wrap under config.