[M] Change in coreboot[main]: soc/intel: Allow zero values for PMC GPE0 DW registers

[Jérémy Compostella (Code Review)]

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Eric Lai, Intel coreboot Reviewers, Jakub Czapiga, Jayvik Desai, Kapil Porwal, Matt DeVillier, Nick Vaccaro, Pranava Y N, Sean Rhodes, Subrata Banik, Tarun, Werner Zeh.

Jérémy Compostella has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/86164?usp=email )

Change subject: soc/intel: Allow zero values for PMC GPE0 DW registers
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Patch Set 5:

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/86164/comment/ba64427e_22a34cea?usp... :
PS2, Line 14: This prevents potential issues arising from a zeroed configuration
> > The commit message still needs some update in my opinion: […]

Thank you fixing the logic. And for the explaining that it avoids an a assertion when platform decides to not configure GPE and use all DWs set to zero value in the commit message.

Commit Message:

https://review.coreboot.org/c/coreboot/+/86164/comment/e27c1eed_3f91921c?usp... :
PS5, Line 21: - **All DWs zero:** A warning message is printed, and the system boots
It is unclear how incorporating markdown syntax enhances the quality of a commit message. From my perspective, this addition may compromise readability, considering commit messages are typically consumed as plain ASCII text. Furthermore, the inclusion of such syntax could potentially complicate search operations within commit messages.