Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/22776 )
Change subject: intel/sandybridge: Make timC training more robust. ......................................................................
Patch Set 3:
(3 comments)
https://review.coreboot.org/#/c/22776/3/src/northbridge/intel/sandybridge/ra... File src/northbridge/intel/sandybridge/raminit_common.c:
https://review.coreboot.org/#/c/22776/3/src/northbridge/intel/sandybridge/ra... PS3, Line 1577: rn.length < 8 Why? 0 errors is 0 errors...
https://review.coreboot.org/#/c/22776/3/src/northbridge/intel/sandybridge/ra... PS3, Line 1578: printk(BIOS_EMERG, "timC discovery failed: %d, %d, %d\n", : channel, slotrank, lane); I'd change the is message.
https://review.coreboot.org/#/c/22776/3/src/northbridge/intel/sandybridge/ra... PS3, Line 1581: avarage The average is a very high since most of the entries will have the max (4000) errors. Would a rather small (let's say 20-50) threshold above the min value not result in better statistics?
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Arthur Heymans (Code Review)