Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48255 )
Change subject: mb/google/zork: Set S0IX_SLP_L high in S0, low in S3 ......................................................................
mb/google/zork: Set S0IX_SLP_L high in S0, low in S3
This is used as a signal to show the system state. It hadn't been used up to this point as we're not currently using S0i3, but the fingerprint sensor will use it to go into a low power mode, so set it appropriately on Trembyle. Dalboz devices don't use the FPMCU, but set there as well so that the state matches.
BUG=b:174695987 TEST=Verify GPIO state in S0 and S3 with the EC BRANCH=Zork
Signed-off-by: Martin Roth martinroth@chromium.org Change-Id: Ibc725905909830d44f77c2498a26edf6d7a3dc05 --- M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c 2 files changed, 8 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/48255/1
diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c index 884862d..a528827 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c @@ -30,8 +30,8 @@ PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE), /* TOUCHPAD_INT_ODL */ PAD_SCI(GPIO_9, PULL_NONE, EDGE_LOW), - /* S0iX SLP - (unused - goes to EC */ - PAD_NC(GPIO_10), + /* S0iX SLP - goes to EC */ + PAD_GPO(GPIO_10, HIGH), /* EC_IN_RW_OD */ PAD_GPI(GPIO_11, PULL_NONE), /* USI_INT_ODL */ @@ -302,6 +302,8 @@ }
static const struct soc_amd_gpio gpio_sleep_table[] = { + /* S0iX SLP */ + PAD_GPO(GPIO_10, LOW), /* PCIE_RST1_L */ PAD_GPO(GPIO_27, LOW), /* diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c index 818c39b..2929c54 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c @@ -32,8 +32,8 @@ PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE), /* TOUCHPAD_INT_ODL */ PAD_SCI(GPIO_9, PULL_NONE, EDGE_LOW), - /* S0iX SLP - (unused - goes to EC & FPMCU */ - PAD_NC(GPIO_10), + /* S0iX SLP - goes to EC & FPMCU */ + PAD_GPO(GPIO_10, HIGH), /* USI_INT_ODL */ PAD_GPI(GPIO_12, PULL_NONE), /* EN_PWR_TOUCHPAD_PS2 */ @@ -342,6 +342,8 @@ }
static const struct soc_amd_gpio gpio_sleep_table[] = { + /* S0iX SLP */ + PAD_GPO(GPIO_10, LOW), /* NVME_AUX_RESET_L */ PAD_GPO(GPIO_40, LOW), /* EN_PWR_CAMERA */
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48255 )
Change subject: mb/google/zork: Set S0IX_SLP_L high in S0, low in S3 ......................................................................
Patch Set 1: Code-Review+1
all variants use the same gpio for that, right?
Vincent Palatin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48255 )
Change subject: mb/google/zork: Set S0IX_SLP_L high in S0, low in S3 ......................................................................
Patch Set 1: Code-Review+1
Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48255 )
Change subject: mb/google/zork: Set S0IX_SLP_L high in S0, low in S3 ......................................................................
Patch Set 1: Code-Review+1
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48255 )
Change subject: mb/google/zork: Set S0IX_SLP_L high in S0, low in S3 ......................................................................
Patch Set 1: Code-Review+2
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48255 )
Change subject: mb/google/zork: Set S0IX_SLP_L high in S0, low in S3 ......................................................................
mb/google/zork: Set S0IX_SLP_L high in S0, low in S3
This is used as a signal to show the system state. It hadn't been used up to this point as we're not currently using S0i3, but the fingerprint sensor will use it to go into a low power mode, so set it appropriately on Trembyle. Dalboz devices don't use the FPMCU, but set there as well so that the state matches.
BUG=b:174695987 TEST=Verify GPIO state in S0 and S3 with the EC BRANCH=Zork
Signed-off-by: Martin Roth martinroth@chromium.org Change-Id: Ibc725905909830d44f77c2498a26edf6d7a3dc05 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48255 Reviewed-by: Felix Held felix-coreboot@felixheld.de Reviewed-by: Vincent Palatin vpalatin@google.com Reviewed-by: Rob Barnes robbarnes@google.com Reviewed-by: Furquan Shaikh furquan@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c M src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c 2 files changed, 8 insertions(+), 4 deletions(-)
Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, but someone else must approve Furquan Shaikh: Looks good to me, approved Vincent Palatin: Looks good to me, but someone else must approve Rob Barnes: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c index 884862d..a528827 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c @@ -30,8 +30,8 @@ PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE), /* TOUCHPAD_INT_ODL */ PAD_SCI(GPIO_9, PULL_NONE, EDGE_LOW), - /* S0iX SLP - (unused - goes to EC */ - PAD_NC(GPIO_10), + /* S0iX SLP - goes to EC */ + PAD_GPO(GPIO_10, HIGH), /* EC_IN_RW_OD */ PAD_GPI(GPIO_11, PULL_NONE), /* USI_INT_ODL */ @@ -302,6 +302,8 @@ }
static const struct soc_amd_gpio gpio_sleep_table[] = { + /* S0iX SLP */ + PAD_GPO(GPIO_10, LOW), /* PCIE_RST1_L */ PAD_GPO(GPIO_27, LOW), /* diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c index 818c39b..2929c54 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c @@ -32,8 +32,8 @@ PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE), /* TOUCHPAD_INT_ODL */ PAD_SCI(GPIO_9, PULL_NONE, EDGE_LOW), - /* S0iX SLP - (unused - goes to EC & FPMCU */ - PAD_NC(GPIO_10), + /* S0iX SLP - goes to EC & FPMCU */ + PAD_GPO(GPIO_10, HIGH), /* USI_INT_ODL */ PAD_GPI(GPIO_12, PULL_NONE), /* EN_PWR_TOUCHPAD_PS2 */ @@ -342,6 +342,8 @@ }
static const struct soc_amd_gpio gpio_sleep_table[] = { + /* S0iX SLP */ + PAD_GPO(GPIO_10, LOW), /* NVME_AUX_RESET_L */ PAD_GPO(GPIO_40, LOW), /* EN_PWR_CAMERA */
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Felix Held (Code Review) -
Furquan Shaikh (Code Review)
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Martin Roth (Code Review)
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Rob Barnes (Code Review)
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Vincent Palatin (Code Review)