[XS] Change in coreboot[main]: soc/intel/mtl: Call cse_fill_bp_info early in romstage

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78056?usp=email )

Change subject: soc/intel/mtl: Call cse_fill_bp_info early in romstage
......................................................................

soc/intel/mtl: Call cse_fill_bp_info early in romstage

Intel Platform Service Record(PSR) will be enabled on Meteor Lake
platforms. cse_fw_sync actions happen in ramstage when PSR is enabled.
To avoid the boot time penalty of sending the cse_get_bp_info in
ramstage, call cse_fill_bp_info to get cse_bp_info response early in
romstage and store in cbmem. This data can be later used in ramstage.

BUG=b:273207144
TEST=Verify cse_bp_info is filled in romstage in rex.

Change-Id: Ic0e8fb34f21ff07e182a7b848d38e9d329010028
Signed-off-by: Krishna Prasad Bhat 
Signed-off-by: Rizwan Qureshi 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78056
Tested-by: build bot (Jenkins) 
Reviewed-by: Anil Kumar K 
Reviewed-by: Subrata Banik 
Reviewed-by: Kapil Porwal 
---
M src/soc/intel/meteorlake/romstage/romstage.c
1 file changed, 5 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Anil Kumar K: Looks good to me, but someone else must approve
  Subrata Banik: Looks good to me, approved
  Kapil Porwal: Looks good to me, approved

diff --git a/src/soc/intel/meteorlake/romstage/romstage.c b/src/soc/intel/meteorlake/romstage/romstage.c
index 3df480c..1f1cfd6 100644
--- a/src/soc/intel/meteorlake/romstage/romstage.c
+++ b/src/soc/intel/meteorlake/romstage/romstage.c
@@ -129,8 +129,11 @@
    /* Initialize HECI interface */
    cse_init(HECI1_BASE_ADDRESS);

-	if (!s3wake && CONFIG(SOC_INTEL_CSE_LITE_SKU))
-		cse_fw_sync();
+	if (!s3wake && CONFIG(SOC_INTEL_CSE_LITE_SKU)) {
+		cse_fill_bp_info();
+		if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE))
+			cse_fw_sync();
+	}

/* Update coreboot timestamp table with CSE timestamps */
    if (CONFIG(SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY))