Mengqi Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32461
Change subject: mediatek: Add SPI tick_dly setting ......................................................................
mediatek: Add SPI tick_dly setting
Add spi tick_dly setting for high-speed spi xfer.
BUG=b:80501386 BRANCH=none TEST=emerge-kukui coreboot; emerge-elm coreboot
Change-Id: Ie49fc3efe2a4a6dcdf2a2fc4c91b47e35d4f086e Signed-off-by: Mengqi Zhang Mengqi.Zhang@mediatek.com --- M src/mainboard/google/kukui/bootblock.c M src/mainboard/google/kukui/early_init.c M src/mainboard/google/oak/bootblock.c M src/soc/mediatek/common/include/soc/spi_common.h M src/soc/mediatek/common/spi.c M src/soc/mediatek/mt8173/include/soc/spi.h M src/soc/mediatek/mt8173/spi.c M src/soc/mediatek/mt8183/include/soc/spi.h M src/soc/mediatek/mt8183/spi.c 9 files changed, 33 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/32461/1
diff --git a/src/mainboard/google/kukui/bootblock.c b/src/mainboard/google/kukui/bootblock.c index 9d6c38b..1efbc7a 100644 --- a/src/mainboard/google/kukui/bootblock.c +++ b/src/mainboard/google/kukui/bootblock.c @@ -18,6 +18,8 @@
void bootblock_mainboard_init(void) { - mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 6 * MHz); - mtk_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, SPI_PAD0_MASK, 26 * MHz); + mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 6 * MHz, + 0); + mtk_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, SPI_PAD0_MASK, 26 * MHz, + 0); } diff --git a/src/mainboard/google/kukui/early_init.c b/src/mainboard/google/kukui/early_init.c index 1193bb3..7eee080 100644 --- a/src/mainboard/google/kukui/early_init.c +++ b/src/mainboard/google/kukui/early_init.c @@ -34,6 +34,6 @@
gpio_set_mode(AP_IN_SLEEP_L, PAD_SRCLKENA0_FUNC_SRCLKENA0);
- mtk_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, SPI_PAD0_MASK, 1 * MHz); + mtk_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0); gpio_eint_configure(CR50_IRQ, IRQ_TYPE_EDGE_RISING); } diff --git a/src/mainboard/google/oak/bootblock.c b/src/mainboard/google/oak/bootblock.c index 3c50389..89169ef 100644 --- a/src/mainboard/google/oak/bootblock.c +++ b/src/mainboard/google/oak/bootblock.c @@ -89,7 +89,8 @@ if (CONFIG(OAK_HAS_TPM2)) gpio_eint_configure(CR50_IRQ, IRQ_TYPE_EDGE_RISING);
- mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD1_MASK, 6*MHz); + mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD1_MASK, 6*MHz, + 0);
setup_chromeos_gpios();
diff --git a/src/soc/mediatek/common/include/soc/spi_common.h b/src/soc/mediatek/common/include/soc/spi_common.h index 162db59..81a9098 100644 --- a/src/soc/mediatek/common/include/soc/spi_common.h +++ b/src/soc/mediatek/common/include/soc/spi_common.h @@ -84,8 +84,9 @@
void mtk_spi_set_gpio_pinmux(unsigned int bus, enum spi_pad_mask pad_select); -void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks); +void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks, + unsigned int tick_dly); void mtk_spi_init(unsigned int bus, enum spi_pad_mask pad_select, - unsigned int speed_hz); + unsigned int speed_hz, unsigned int tick_dly);
#endif diff --git a/src/soc/mediatek/common/spi.c b/src/soc/mediatek/common/spi.c index 71ed95a..1af6f10 100644 --- a/src/soc/mediatek/common/spi.c +++ b/src/soc/mediatek/common/spi.c @@ -53,7 +53,7 @@ }
void mtk_spi_init(unsigned int bus, enum spi_pad_mask pad_select, - unsigned int speed_hz) + unsigned int speed_hz, unsigned int tick_dly) { u32 div, sck_ticks, cs_ticks;
@@ -73,7 +73,7 @@ printk(BIOS_DEBUG, "SPI%u(PAD%u) initialized at %u Hz\n", bus, pad_select, SPI_HZ / (sck_ticks * 2));
- mtk_spi_set_timing(regs, sck_ticks, cs_ticks); + mtk_spi_set_timing(regs, sck_ticks, cs_ticks, tick_dly);
clrsetbits_le32(®s->spi_cmd_reg, (SPI_CMD_CPHA_EN | SPI_CMD_CPOL_EN | diff --git a/src/soc/mediatek/mt8173/include/soc/spi.h b/src/soc/mediatek/mt8173/include/soc/spi.h index aaef3aa..525f160 100644 --- a/src/soc/mediatek/mt8173/include/soc/spi.h +++ b/src/soc/mediatek/mt8173/include/soc/spi.h @@ -43,4 +43,10 @@ SPI_CFG0_CS_SETUP_SHIFT = 24, };
+enum { + SPI_CFG1_TICK_DLY_SHIFT = 30, + + SPI_CFG1_TICK_DLY_MASK = 0x3 << SPI_CFG1_TICK_DLY_SHIFT, +}; + #endif diff --git a/src/soc/mediatek/mt8173/spi.c b/src/soc/mediatek/mt8173/spi.c index 0cc8377..d009441 100644 --- a/src/soc/mediatek/mt8173/spi.c +++ b/src/soc/mediatek/mt8173/spi.c @@ -38,14 +38,17 @@ gpio_set_mode(GPIO(MSDC2_CMD), PAD_MSDC2_CMD_FUNC_SPI_CS_1); }
-void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks) +void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks, + unsigned int tick_dly) { write32(®s->spi_cfg0_reg, ((sck_ticks - 1) << SPI_CFG0_SCK_HIGH_SHIFT) | ((sck_ticks - 1) << SPI_CFG0_SCK_LOW_SHIFT) | ((cs_ticks - 1) << SPI_CFG0_CS_HOLD_SHIFT) | ((cs_ticks - 1) << SPI_CFG0_CS_SETUP_SHIFT)); - clrsetbits_le32(®s->spi_cfg1_reg, SPI_CFG1_CS_IDLE_MASK, + clrsetbits_le32(®s->spi_cfg1_reg, SPI_CFG1_CS_IDLE_MASK | + SPI_CFG1_TICK_DLY_MASK, + (tick_dly << SPI_CFG1_TICK_DLY_SHIFT) | ((cs_ticks - 1) << SPI_CFG1_CS_IDLE_SHIFT)); }
diff --git a/src/soc/mediatek/mt8183/include/soc/spi.h b/src/soc/mediatek/mt8183/include/soc/spi.h index 9bc7121..dd63e91 100644 --- a/src/soc/mediatek/mt8183/include/soc/spi.h +++ b/src/soc/mediatek/mt8183/include/soc/spi.h @@ -49,5 +49,11 @@ SPI_CFG2_SCK_HIGH_SHIFT = 16, };
+enum { + SPI_CFG1_TICK_DLY_SHIFT = 29, + + SPI_CFG1_TICK_DLY_MASK = 0x7 << SPI_CFG1_TICK_DLY_SHIFT, + +};
#endif diff --git a/src/soc/mediatek/mt8183/spi.c b/src/soc/mediatek/mt8183/spi.c index a79dafb..c57e60f 100644 --- a/src/soc/mediatek/mt8183/spi.c +++ b/src/soc/mediatek/mt8183/spi.c @@ -109,7 +109,8 @@ gpio_set_mode((gpio_t){.id = ptr[i].pin_id}, ptr[i].func); }
-void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks) +void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks, + unsigned int tick_dly) { write32(®s->spi_cfg0_reg, ((cs_ticks - 1) << SPI_CFG0_CS_HOLD_SHIFT) | @@ -119,6 +120,8 @@ ((sck_ticks - 1) << SPI_CFG2_SCK_HIGH_SHIFT) | ((sck_ticks - 1) << SPI_CFG2_SCK_LOW_SHIFT));
+ clrsetbits_le32(®s->spi_cfg1_reg, SPI_CFG1_TICK_DLY_MASK, + tick_dly << SPI_CFG1_TICK_DLY_SHIFT); clrsetbits_le32(®s->spi_cfg1_reg, SPI_CFG1_CS_IDLE_MASK, ((cs_ticks - 1) << SPI_CFG1_CS_IDLE_SHIFT)); }
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32461 )
Change subject: mediatek: Add SPI tick_dly setting ......................................................................
Patch Set 1: Code-Review+1
(2 comments)
https://review.coreboot.org/#/c/32461/1/src/soc/mediatek/mt8173/include/soc/... File src/soc/mediatek/mt8173/include/soc/spi.h:
https://review.coreboot.org/#/c/32461/1/src/soc/mediatek/mt8173/include/soc/... PS1, Line 48: remove the extra blank line
https://review.coreboot.org/#/c/32461/1/src/soc/mediatek/mt8183/include/soc/... File src/soc/mediatek/mt8183/include/soc/spi.h:
https://review.coreboot.org/#/c/32461/1/src/soc/mediatek/mt8183/include/soc/... PS1, Line 54: remove the extra blank line
Hello Julius Werner, You-Cheng Syu, Tristan Hsieh, Hung-Te Lin, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32461
to look at the new patch set (#2).
Change subject: mediatek: Add SPI tick_dly setting ......................................................................
mediatek: Add SPI tick_dly setting
Add spi tick_dly setting for high-speed spi xfer.
BUG=b:80501386 BRANCH=none TEST=emerge-kukui coreboot; emerge-elm coreboot
Change-Id: Ie49fc3efe2a4a6dcdf2a2fc4c91b47e35d4f086e Signed-off-by: Mengqi Zhang Mengqi.Zhang@mediatek.com --- M src/mainboard/google/kukui/bootblock.c M src/mainboard/google/kukui/early_init.c M src/mainboard/google/oak/bootblock.c M src/soc/mediatek/common/include/soc/spi_common.h M src/soc/mediatek/common/spi.c M src/soc/mediatek/mt8173/include/soc/spi.h M src/soc/mediatek/mt8173/spi.c M src/soc/mediatek/mt8183/include/soc/spi.h M src/soc/mediatek/mt8183/spi.c 9 files changed, 31 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/32461/2
Mengqi Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32461 )
Change subject: mediatek: Add SPI tick_dly setting ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/#/c/32461/1/src/soc/mediatek/mt8173/include/soc/... File src/soc/mediatek/mt8173/include/soc/spi.h:
https://review.coreboot.org/#/c/32461/1/src/soc/mediatek/mt8173/include/soc/... PS1, Line 48:
remove the extra blank line
Done
https://review.coreboot.org/#/c/32461/1/src/soc/mediatek/mt8183/include/soc/... File src/soc/mediatek/mt8183/include/soc/spi.h:
https://review.coreboot.org/#/c/32461/1/src/soc/mediatek/mt8183/include/soc/... PS1, Line 54:
remove the extra blank line
Done
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32461 )
Change subject: mediatek: Add SPI tick_dly setting ......................................................................
Patch Set 2: Code-Review+1
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32461 )
Change subject: mediatek: Add SPI tick_dly setting ......................................................................
Patch Set 2: Code-Review+2
(1 comment)
https://review.coreboot.org/#/c/32461/2/src/soc/mediatek/mt8183/spi.c File src/soc/mediatek/mt8183/spi.c:
https://review.coreboot.org/#/c/32461/2/src/soc/mediatek/mt8183/spi.c@125 PS2, Line 125: clrsetbits_le32(®s->spi_cfg1_reg, SPI_CFG1_CS_IDLE_MASK, nit: merge both into a single clrsetbits_le32() like you did for the 8173 case?
Hello Julius Werner, You-Cheng Syu, Tristan Hsieh, Hung-Te Lin, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32461
to look at the new patch set (#3).
Change subject: mediatek: Add SPI tick_dly setting ......................................................................
mediatek: Add SPI tick_dly setting
Add spi tick_dly setting for high-speed spi xfer.
BUG=b:80501386 BRANCH=none TEST=emerge-kukui coreboot; emerge-elm coreboot
Change-Id: Ie49fc3efe2a4a6dcdf2a2fc4c91b47e35d4f086e Signed-off-by: Mengqi Zhang Mengqi.Zhang@mediatek.com --- M src/mainboard/google/kukui/bootblock.c M src/mainboard/google/kukui/early_init.c M src/mainboard/google/oak/bootblock.c M src/soc/mediatek/common/include/soc/spi_common.h M src/soc/mediatek/common/spi.c M src/soc/mediatek/mt8173/include/soc/spi.h M src/soc/mediatek/mt8173/spi.c M src/soc/mediatek/mt8183/include/soc/spi.h M src/soc/mediatek/mt8183/spi.c 9 files changed, 33 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/32461/3
Mengqi Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32461 )
Change subject: mediatek: Add SPI tick_dly setting ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/32461/2/src/soc/mediatek/mt8183/spi.c File src/soc/mediatek/mt8183/spi.c:
https://review.coreboot.org/#/c/32461/2/src/soc/mediatek/mt8183/spi.c@125 PS2, Line 125: clrsetbits_le32(®s->spi_cfg1_reg, SPI_CFG1_CS_IDLE_MASK,
nit: merge both into a single clrsetbits_le32() like you did for the 8173 case?
Done
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32461 )
Change subject: mediatek: Add SPI tick_dly setting ......................................................................
Patch Set 3: Code-Review+2
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32461 )
Change subject: mediatek: Add SPI tick_dly setting ......................................................................
mediatek: Add SPI tick_dly setting
Add spi tick_dly setting for high-speed spi xfer.
BUG=b:80501386 BRANCH=none TEST=emerge-kukui coreboot; emerge-elm coreboot
Change-Id: Ie49fc3efe2a4a6dcdf2a2fc4c91b47e35d4f086e Signed-off-by: Mengqi Zhang Mengqi.Zhang@mediatek.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/32461 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Julius Werner jwerner@chromium.org --- M src/mainboard/google/kukui/bootblock.c M src/mainboard/google/kukui/early_init.c M src/mainboard/google/oak/bootblock.c M src/soc/mediatek/common/include/soc/spi_common.h M src/soc/mediatek/common/spi.c M src/soc/mediatek/mt8173/include/soc/spi.h M src/soc/mediatek/mt8173/spi.c M src/soc/mediatek/mt8183/include/soc/spi.h M src/soc/mediatek/mt8183/spi.c 9 files changed, 33 insertions(+), 12 deletions(-)
Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved
diff --git a/src/mainboard/google/kukui/bootblock.c b/src/mainboard/google/kukui/bootblock.c index 9a7e71c..ebd1e18 100644 --- a/src/mainboard/google/kukui/bootblock.c +++ b/src/mainboard/google/kukui/bootblock.c @@ -19,8 +19,11 @@
void bootblock_mainboard_init(void) { - mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 6 * MHz); - mtk_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, SPI_PAD0_MASK, 26 * MHz); + mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 6 * MHz, + 0); + mtk_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, SPI_PAD0_MASK, 26 * MHz, + 0); gpio_set_spi_driving(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, SPI_PAD0_MASK, 10); + } diff --git a/src/mainboard/google/kukui/early_init.c b/src/mainboard/google/kukui/early_init.c index 1193bb3..7eee080 100644 --- a/src/mainboard/google/kukui/early_init.c +++ b/src/mainboard/google/kukui/early_init.c @@ -34,6 +34,6 @@
gpio_set_mode(AP_IN_SLEEP_L, PAD_SRCLKENA0_FUNC_SRCLKENA0);
- mtk_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, SPI_PAD0_MASK, 1 * MHz); + mtk_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0); gpio_eint_configure(CR50_IRQ, IRQ_TYPE_EDGE_RISING); } diff --git a/src/mainboard/google/oak/bootblock.c b/src/mainboard/google/oak/bootblock.c index 3c50389..89169ef 100644 --- a/src/mainboard/google/oak/bootblock.c +++ b/src/mainboard/google/oak/bootblock.c @@ -89,7 +89,8 @@ if (CONFIG(OAK_HAS_TPM2)) gpio_eint_configure(CR50_IRQ, IRQ_TYPE_EDGE_RISING);
- mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD1_MASK, 6*MHz); + mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD1_MASK, 6*MHz, + 0);
setup_chromeos_gpios();
diff --git a/src/soc/mediatek/common/include/soc/spi_common.h b/src/soc/mediatek/common/include/soc/spi_common.h index 162db59..81a9098 100644 --- a/src/soc/mediatek/common/include/soc/spi_common.h +++ b/src/soc/mediatek/common/include/soc/spi_common.h @@ -84,8 +84,9 @@
void mtk_spi_set_gpio_pinmux(unsigned int bus, enum spi_pad_mask pad_select); -void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks); +void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks, + unsigned int tick_dly); void mtk_spi_init(unsigned int bus, enum spi_pad_mask pad_select, - unsigned int speed_hz); + unsigned int speed_hz, unsigned int tick_dly);
#endif diff --git a/src/soc/mediatek/common/spi.c b/src/soc/mediatek/common/spi.c index 71ed95a..1af6f10 100644 --- a/src/soc/mediatek/common/spi.c +++ b/src/soc/mediatek/common/spi.c @@ -53,7 +53,7 @@ }
void mtk_spi_init(unsigned int bus, enum spi_pad_mask pad_select, - unsigned int speed_hz) + unsigned int speed_hz, unsigned int tick_dly) { u32 div, sck_ticks, cs_ticks;
@@ -73,7 +73,7 @@ printk(BIOS_DEBUG, "SPI%u(PAD%u) initialized at %u Hz\n", bus, pad_select, SPI_HZ / (sck_ticks * 2));
- mtk_spi_set_timing(regs, sck_ticks, cs_ticks); + mtk_spi_set_timing(regs, sck_ticks, cs_ticks, tick_dly);
clrsetbits_le32(®s->spi_cmd_reg, (SPI_CMD_CPHA_EN | SPI_CMD_CPOL_EN | diff --git a/src/soc/mediatek/mt8173/include/soc/spi.h b/src/soc/mediatek/mt8173/include/soc/spi.h index aaef3aa..58bf517 100644 --- a/src/soc/mediatek/mt8173/include/soc/spi.h +++ b/src/soc/mediatek/mt8173/include/soc/spi.h @@ -43,4 +43,9 @@ SPI_CFG0_CS_SETUP_SHIFT = 24, };
+enum { + SPI_CFG1_TICK_DLY_SHIFT = 30, + SPI_CFG1_TICK_DLY_MASK = 0x3 << SPI_CFG1_TICK_DLY_SHIFT, +}; + #endif diff --git a/src/soc/mediatek/mt8173/spi.c b/src/soc/mediatek/mt8173/spi.c index 0cc8377..d009441 100644 --- a/src/soc/mediatek/mt8173/spi.c +++ b/src/soc/mediatek/mt8173/spi.c @@ -38,14 +38,17 @@ gpio_set_mode(GPIO(MSDC2_CMD), PAD_MSDC2_CMD_FUNC_SPI_CS_1); }
-void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks) +void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks, + unsigned int tick_dly) { write32(®s->spi_cfg0_reg, ((sck_ticks - 1) << SPI_CFG0_SCK_HIGH_SHIFT) | ((sck_ticks - 1) << SPI_CFG0_SCK_LOW_SHIFT) | ((cs_ticks - 1) << SPI_CFG0_CS_HOLD_SHIFT) | ((cs_ticks - 1) << SPI_CFG0_CS_SETUP_SHIFT)); - clrsetbits_le32(®s->spi_cfg1_reg, SPI_CFG1_CS_IDLE_MASK, + clrsetbits_le32(®s->spi_cfg1_reg, SPI_CFG1_CS_IDLE_MASK | + SPI_CFG1_TICK_DLY_MASK, + (tick_dly << SPI_CFG1_TICK_DLY_SHIFT) | ((cs_ticks - 1) << SPI_CFG1_CS_IDLE_SHIFT)); }
diff --git a/src/soc/mediatek/mt8183/include/soc/spi.h b/src/soc/mediatek/mt8183/include/soc/spi.h index 9bc7121..f718081 100644 --- a/src/soc/mediatek/mt8183/include/soc/spi.h +++ b/src/soc/mediatek/mt8183/include/soc/spi.h @@ -49,5 +49,10 @@ SPI_CFG2_SCK_HIGH_SHIFT = 16, };
+enum { + SPI_CFG1_TICK_DLY_SHIFT = 29, + SPI_CFG1_TICK_DLY_MASK = 0x7 << SPI_CFG1_TICK_DLY_SHIFT, + +};
#endif diff --git a/src/soc/mediatek/mt8183/spi.c b/src/soc/mediatek/mt8183/spi.c index a79dafb..982f643 100644 --- a/src/soc/mediatek/mt8183/spi.c +++ b/src/soc/mediatek/mt8183/spi.c @@ -109,7 +109,8 @@ gpio_set_mode((gpio_t){.id = ptr[i].pin_id}, ptr[i].func); }
-void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks) +void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks, + unsigned int tick_dly) { write32(®s->spi_cfg0_reg, ((cs_ticks - 1) << SPI_CFG0_CS_HOLD_SHIFT) | @@ -119,7 +120,9 @@ ((sck_ticks - 1) << SPI_CFG2_SCK_HIGH_SHIFT) | ((sck_ticks - 1) << SPI_CFG2_SCK_LOW_SHIFT));
- clrsetbits_le32(®s->spi_cfg1_reg, SPI_CFG1_CS_IDLE_MASK, + clrsetbits_le32(®s->spi_cfg1_reg, SPI_CFG1_TICK_DLY_MASK | + SPI_CFG1_CS_IDLE_MASK, + (tick_dly << SPI_CFG1_TICK_DLY_SHIFT) | ((cs_ticks - 1) << SPI_CFG1_CS_IDLE_SHIFT)); }
-
Hung-Te Lin (Code Review) -
Julius Werner (Code Review)
-
Mengqi Zhang (Code Review)
-
Patrick Georgi (Code Review)