Change in ...coreboot[master]: mb/google/{arcada, hatch, sarien}: Override FSP default GPIO PM confi...
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32848
Change subject: mb/google/{arcada, hatch, sarien}: Override FSP default GPIO PM configuration ......................................................................
mb/google/{arcada, hatch, sarien}: Override FSP default GPIO PM configuration
sarien/arcada:
GPIO_COMM_0/2/3/4: Enable gpio community all PM configuration GPIO_COMM_1: Disable RCOMP clock gating
hatch:
GPIO_COMM_0/1/2/3: Enable gpio community all PM configuration GPIO_COMM_4: Disable RCOMP clock gating
Change-Id: Ia4d5483847a4d243b9038119d4bb5990591cc754 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb 3 files changed, 30 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/32848/1
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 09e004e..9d10cac 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -89,6 +89,16 @@ register "PchHdaAudioLinkSsp1" = "1" register "PchHdaAudioLinkDmic0" = "1"
+ # GPIO PM programming + register "gpio_override_pm" = "1" + + # GPIO community PM configuration + register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_1]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_4]" = "MISCCFG_GPSIDEDPCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN" + device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index b6377ba..d3848a2 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -201,6 +201,16 @@ register "PcieClkSrcUsage[4]" = "12" register "PcieClkSrcClkReq[4]" = "4"
+ # GPIO PM programming + register "gpio_override_pm" = "1" + + # GPIO community PM configuration + register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_1]" = "MISCCFG_GPSIDEDPCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN" + register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_4]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 3807047..c96423c 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -205,6 +205,16 @@ register "PcieClkSrcUsage[2]" = "12" register "PcieClkSrcClkReq[2]" = "2"
+ # GPIO PM programming + register "gpio_override_pm" = "1" + + # GPIO community PM configuration + register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_1]" = "MISCCFG_GPSIDEDPCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN" + register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_4]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + device cpu_cluster 0 on device lapic 0 on end end
Hello Aaron Durbin, Rizwan Qureshi, Bora Guvendik, V Sowmya, Lijian Zhao, Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32848
to look at the new patch set (#2).
Change subject: mb/google/{arcada, hatch, sarien}: Override FSP default GPIO PM configuration ......................................................................
mb/google/{arcada, hatch, sarien}: Override FSP default GPIO PM configuration
sarien/arcada:
GPIO_COMM_0/2/3/4: Enable gpio community all PM configuration GPIO_COMM_1: Disable RCOMP clock gating due to GPP_D18 IRQ mapped for H1 TPM.
hatch:
GPIO_COMM_0/1/2/3: Enable gpio community all PM configuration GPIO_COMM_4: Disable RCOMP clock gating due to GPP_C21 IRQ mapped for H1 TPM.
Change-Id: Ia4d5483847a4d243b9038119d4bb5990591cc754 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb 3 files changed, 30 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/32848/2
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32848 )
Change subject: mb/google/{arcada, hatch, sarien}: Override FSP default GPIO PM configuration ......................................................................
Patch Set 2:
Furquan, without this CL, we can't merge the other one as it will cause boot regression. please help to review this as well
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32848 )
Change subject: mb/google/{arcada, hatch, sarien}: Override FSP default GPIO PM configuration ......................................................................
Patch Set 2: Code-Review+1
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32848 )
Change subject: mb/google/{arcada, hatch, sarien}: Override FSP default GPIO PM configuration ......................................................................
Patch Set 2: Code-Review+2
(1 comment)
https://review.coreboot.org/#/c/32848/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/32848/2//COMMIT_MSG@18 PS2, Line 18: TEST=?
H1 interrupt works fine? Any other regression observed in dmesg/coreboot logs?
Hello Aaron Durbin, Aamir Bohra, Duncan Laurie, Rizwan Qureshi, Bora Guvendik, V Sowmya, build bot (Jenkins), Lijian Zhao, Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32848
to look at the new patch set (#3).
Change subject: mb/google/{arcada, hatch, sarien}: Override FSP default GPIO PM configuration ......................................................................
mb/google/{arcada, hatch, sarien}: Override FSP default GPIO PM configuration
sarien/arcada:
GPIO_COMM_0/2/3/4: Enable gpio community all PM configuration GPIO_COMM_1: Disable RCOMP clock gating due to GPP_D18 IRQ mapped for H1 TPM.
hatch:
GPIO_COMM_0/1/2/3: Enable gpio community all PM configuration GPIO_COMM_4: Disable RCOMP clock gating due to GPP_C21 IRQ mapped for H1 TPM.
BUG=b:130764684 TEST=H1 TPM interrupt working find and able to boot from fixed boot media
Change-Id: Ia4d5483847a4d243b9038119d4bb5990591cc754 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb 3 files changed, 30 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/32848/3
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32848 )
Change subject: mb/google/{arcada, hatch, sarien}: Override FSP default GPIO PM configuration ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/32848/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/32848/2//COMMIT_MSG@18 PS2, Line 18:
TEST=? […]
Done
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32848 )
Change subject: mb/google/{arcada, hatch, sarien}: Override FSP default GPIO PM configuration ......................................................................
Patch Set 3:
may be you need to check this CL one more time as +2 gone after modifying commit msg :(
i have request Sowmya to verify this CL again and share feedback before merging
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32848 )
Change subject: mb/google/{arcada, hatch, sarien}: Override FSP default GPIO PM configuration ......................................................................
Patch Set 3: Code-Review+2
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32848 )
Change subject: mb/google/{arcada, hatch, sarien}: Override FSP default GPIO PM configuration ......................................................................
mb/google/{arcada, hatch, sarien}: Override FSP default GPIO PM configuration
sarien/arcada:
GPIO_COMM_0/2/3/4: Enable gpio community all PM configuration GPIO_COMM_1: Disable RCOMP clock gating due to GPP_D18 IRQ mapped for H1 TPM.
hatch:
GPIO_COMM_0/1/2/3: Enable gpio community all PM configuration GPIO_COMM_4: Disable RCOMP clock gating due to GPP_C21 IRQ mapped for H1 TPM.
BUG=b:130764684 TEST=H1 TPM interrupt working find and able to boot from fixed boot media
Change-Id: Ia4d5483847a4d243b9038119d4bb5990591cc754 Signed-off-by: Subrata Banik subrata.banik@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/32848 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb 3 files changed, 30 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 09e004e..9d10cac 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -89,6 +89,16 @@ register "PchHdaAudioLinkSsp1" = "1" register "PchHdaAudioLinkDmic0" = "1"
+ # GPIO PM programming + register "gpio_override_pm" = "1" + + # GPIO community PM configuration + register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_1]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_4]" = "MISCCFG_GPSIDEDPCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN" + device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index b6377ba..d3848a2 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -201,6 +201,16 @@ register "PcieClkSrcUsage[4]" = "12" register "PcieClkSrcClkReq[4]" = "4"
+ # GPIO PM programming + register "gpio_override_pm" = "1" + + # GPIO community PM configuration + register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_1]" = "MISCCFG_GPSIDEDPCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN" + register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_4]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 3807047..c96423c 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -205,6 +205,16 @@ register "PcieClkSrcUsage[2]" = "12" register "PcieClkSrcClkReq[2]" = "2"
+ # GPIO PM programming + register "gpio_override_pm" = "1" + + # GPIO community PM configuration + register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_1]" = "MISCCFG_GPSIDEDPCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN" + register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_4]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + device cpu_cluster 0 on device lapic 0 on end end
-
Aamir Bohra (Code Review) -
Furquan Shaikh (Code Review)
-
Patrick Georgi (Code Review)
-
Subrata Banik (Code Review)