Sergej Ivanov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37719 )
Change subject: biostar/am1ml: Switch away from ROMCC_BOOTBLOCK ......................................................................
biostar/am1ml: Switch away from ROMCC_BOOTBLOCK
Signed-off-by: Sergej Ivanov getinaks@gmail.com Change-Id: I7a972b531183b08af7b325bd686cf3eb7558082f --- A src/mainboard/biostar/am1ml/bootblock.c D src/mainboard/biostar/am1ml/romstage.c 2 files changed, 103 insertions(+), 139 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/37719/1
diff --git a/src/mainboard/biostar/am1ml/bootblock.c b/src/mainboard/biostar/am1ml/bootblock.c new file mode 100644 index 0000000..b5ce761 --- /dev/null +++ b/src/mainboard/biostar/am1ml/bootblock.c @@ -0,0 +1,103 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <amdblocks/acpimmio.h> +#include <bootblock_common.h> +#include <device/pnp_ops.h> +#include <device/pci_ops.h> +#include <superio/ite/common/ite.h> +#include <superio/ite/it8728f/it8728f.h> + +#define SERIAL_DEV PNP_DEV(0x2e, IT8728F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8728F_GPIO) +#define ENVC_DEV PNP_DEV(0x2e, IT8728F_EC) + +static void ite_evc_conf(pnp_devfn_t dev) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_write_config(dev, 0xf1, 0x40); + pnp_write_config(dev, 0xf4, 0x80); + pnp_write_config(dev, 0xf5, 0x00); + pnp_write_config(dev, 0xf6, 0xf0); + pnp_write_config(dev, 0xf9, 0x48); + pnp_write_config(dev, 0xfa, 0x00); + pnp_write_config(dev, 0xfb, 0x00); + pnp_exit_conf_state(dev); +} + +static void ite_gpio_conf(pnp_devfn_t dev) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_write_config(dev, 0x25, 0x80); + pnp_write_config(dev, 0x26, 0x07); + pnp_write_config(dev, 0x28, 0x81); + pnp_write_config(dev, 0x2c, 0x06); + pnp_write_config(dev, 0x72, 0x00); + pnp_write_config(dev, 0x73, 0x00); + pnp_write_config(dev, 0xb3, 0x01); + pnp_write_config(dev, 0xb8, 0x00); + pnp_write_config(dev, 0xc0, 0x00); + pnp_write_config(dev, 0xc3, 0x00); + pnp_write_config(dev, 0xc8, 0x00); + pnp_write_config(dev, 0xc9, 0x07); + pnp_write_config(dev, 0xcb, 0x01); + pnp_write_config(dev, 0xf0, 0x10); + pnp_write_config(dev, 0xf4, 0x27); + pnp_write_config(dev, 0xf8, 0x20); + pnp_write_config(dev, 0xf9, 0x01); + pnp_exit_conf_state(dev); +} + +void bootblock_mainboard_early_init(void) +{ + volatile u32 *addr32; + pci_devfn_t dev; + u32 t32; + u8 byte; + + /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */ + pm_write8(0xea, 0x1); + + /* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */ + addr32 = (u32 *)0xfed80e28; + t32 = *addr32; + t32 &= 0xfff8ffff; + *addr32 = t32; + + /* Enable Auxiliary Clock1, disable FCH 14 MHz OscClk */ + addr32 = (u32 *)0xfed80e40; + t32 = *addr32; + t32 &= 0xffffbffb; + *addr32 = t32; + + /* Enable serial decode */ + dev = PCI_DEV(0, 0x14, 3); + byte = pci_read_config8(dev, 0x44); + byte |= (1 << 6); /* 0x3f8 */ + pci_write_config8(dev, 0x44, byte); + + /* Configure SIO as made under vendor BIOS */ + ite_evc_conf(ENVC_DEV); + ite_gpio_conf(GPIO_DEV); + + + /* Kill watchdog and enable serial output to COM1 */ + ite_kill_watchdog(GPIO_DEV); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + + /* Enable serial output on it8728f */ + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/biostar/am1ml/romstage.c b/src/mainboard/biostar/am1ml/romstage.c deleted file mode 100644 index 6c1581b..0000000 --- a/src/mainboard/biostar/am1ml/romstage.c +++ /dev/null @@ -1,139 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Sergej Ivanov getinaks@gmail.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <device/pnp_ops.h> -#include <device/pci_ops.h> -#include <console/console.h> -#include <northbridge/amd/agesa/state_machine.h> -#include <southbridge/amd/common/amd_defs.h> -#include <southbridge/amd/agesa/hudson/hudson.h> -#include <superio/ite/common/ite.h> -#include <superio/ite/it8728f/it8728f.h> - -#define SERIAL_DEV PNP_DEV(0x2e, IT8728F_SP1) -#define GPIO_DEV PNP_DEV(0x2e, IT8728F_GPIO) -#define ENVC_DEV PNP_DEV(0x2e, IT8728F_EC) - -#define MMIO_NON_POSTED_START 0xfed00000 -#define MMIO_NON_POSTED_END 0xfedfffff -#define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 + (x)) - -static void ite_evc_conf(pnp_devfn_t dev) -{ - pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_write_config(dev, 0xf1, 0x40); - pnp_write_config(dev, 0xf4, 0x80); - pnp_write_config(dev, 0xf5, 0x00); - pnp_write_config(dev, 0xf6, 0xf0); - pnp_write_config(dev, 0xf9, 0x48); - pnp_write_config(dev, 0xfa, 0x00); - pnp_write_config(dev, 0xfb, 0x00); - pnp_exit_conf_state(dev); -} - -static void ite_gpio_conf(pnp_devfn_t dev) -{ - pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_write_config(dev, 0x25, 0x80); - pnp_write_config(dev, 0x26, 0x07); - pnp_write_config(dev, 0x28, 0x81); - pnp_write_config(dev, 0x2c, 0x06); - pnp_write_config(dev, 0x72, 0x00); - pnp_write_config(dev, 0x73, 0x00); - pnp_write_config(dev, 0xb3, 0x01); - pnp_write_config(dev, 0xb8, 0x00); - pnp_write_config(dev, 0xc0, 0x00); - pnp_write_config(dev, 0xc3, 0x00); - pnp_write_config(dev, 0xc8, 0x00); - pnp_write_config(dev, 0xc9, 0x07); - pnp_write_config(dev, 0xcb, 0x01); - pnp_write_config(dev, 0xf0, 0x10); - pnp_write_config(dev, 0xf4, 0x27); - pnp_write_config(dev, 0xf8, 0x20); - pnp_write_config(dev, 0xf9, 0x01); - pnp_exit_conf_state(dev); -} - -void board_BeforeAgesa(struct sysinfo *cb) -{ - u32 val, t32; - u8 byte; - pci_devfn_t dev; - u32 *addr32; - - /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for - * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA - * even though the register is not documented in the Kabini BKDG. - * Otherwise the serial output is bad code. - */ - outb(0xD2, 0xcd6); - outb(0x00, 0xcd7); - - /* Set LPC decode enables. */ - pci_devfn_t dev2 = PCI_DEV(0, 0x14, 3); - pci_write_config32(dev2, 0x44, 0xff03ffd5); - - /* Enable the AcpiMmio space */ - outb(0x24, 0xcd6); - outb(0x1, 0xcd7); - - /* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */ - addr32 = (u32 *)0xfed80e28; - t32 = *addr32; - t32 &= 0xfff8ffff; - *addr32 = t32; - - /* Enable Auxiliary Clock1, disable FCH 14 MHz OscClk */ - addr32 = (u32 *)0xfed80e40; - t32 = *addr32; - t32 &= 0xffffbffb; - *addr32 = t32; - - /* enable SIO LPC decode */ - dev = PCI_DEV(0, 0x14, 3); - byte = pci_read_config8(dev, 0x48); - byte |= 3; /* 2e, 2f */ - pci_write_config8(dev, 0x48, byte); - - /* enable serial decode */ - byte = pci_read_config8(dev, 0x44); - byte |= (1 << 6); /* 0x3f8 */ - pci_write_config8(dev, 0x44, byte); - - /* This functions configure SIO as it been done under vendor bios */ - printk(BIOS_DEBUG, "ITE CONFIG ENVC\n"); - ite_evc_conf(ENVC_DEV); - printk(BIOS_DEBUG, "ITE CONFIG GPIO\n"); - ite_gpio_conf(GPIO_DEV); - printk(BIOS_DEBUG, "ITE CONFIG DONE\n"); - - - ite_kill_watchdog(GPIO_DEV); - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ - int i; - for (i = 0; i < 200000; i++) - val = inb(0xcd6); - - outb(0xEA, 0xCD6); - outb(0x1, 0xcd7); - - post_code(0x50); -}
Sergej Ivanov has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/37719 )
Change subject: biostar/am1ml: Switch away from ROMCC_BOOTBLOCK ......................................................................
biostar/am1ml: Switch away from ROMCC_BOOTBLOCK
Signed-off-by: Sergej Ivanov getinaks@gmail.com Change-Id: I7a972b531183b08af7b325bd686cf3eb7558082f Signed-off-by: Sergej Ivanov getinaks@gmail.com --- M src/mainboard/biostar/am1ml/Kconfig M src/mainboard/biostar/am1ml/Makefile.inc A src/mainboard/biostar/am1ml/bootblock.c D src/mainboard/biostar/am1ml/romstage.c 4 files changed, 105 insertions(+), 140 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/37719/2
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37719 )
Change subject: biostar/am1ml: Switch away from ROMCC_BOOTBLOCK ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/37719/2/src/mainboard/biostar/am1ml... File src/mainboard/biostar/am1ml/bootblock.c:
https://review.coreboot.org/c/coreboot/+/37719/2/src/mainboard/biostar/am1ml... PS2, Line 85: /* Enable serial decode */ already done in hudson_lpc_decode()
https://review.coreboot.org/c/coreboot/+/37719/2/src/mainboard/biostar/am1ml... PS2, Line 102: ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); duplicate of two lines above
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37719
to look at the new patch set (#3).
Change subject: biostar/am1ml: Switch away from ROMCC_BOOTBLOCK ......................................................................
biostar/am1ml: Switch away from ROMCC_BOOTBLOCK
Signed-off-by: Sergej Ivanov getinaks@gmail.com Change-Id: I7a972b531183b08af7b325bd686cf3eb7558082f Signed-off-by: Sergej Ivanov getinaks@gmail.com --- M src/mainboard/biostar/am1ml/Kconfig M src/mainboard/biostar/am1ml/Makefile.inc A src/mainboard/biostar/am1ml/bootblock.c D src/mainboard/biostar/am1ml/romstage.c 4 files changed, 90 insertions(+), 140 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/37719/3
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37719 )
Change subject: biostar/am1ml: Switch away from ROMCC_BOOTBLOCK ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37719/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/37719/3//COMMIT_MSG@12 PS3, Line 12: Remove duplicate sign-off.
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37719
to look at the new patch set (#4).
Change subject: biostar/am1ml: Switch away from ROMCC_BOOTBLOCK ......................................................................
biostar/am1ml: Switch away from ROMCC_BOOTBLOCK
Change-Id: I7a972b531183b08af7b325bd686cf3eb7558082f Signed-off-by: Sergej Ivanov getinaks@gmail.com --- M src/mainboard/biostar/am1ml/Kconfig M src/mainboard/biostar/am1ml/Makefile.inc A src/mainboard/biostar/am1ml/bootblock.c D src/mainboard/biostar/am1ml/romstage.c 4 files changed, 90 insertions(+), 140 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/37719/4
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37719 )
Change subject: biostar/am1ml: Switch away from ROMCC_BOOTBLOCK ......................................................................
Patch Set 4:
(3 comments)
https://review.coreboot.org/c/coreboot/+/37719/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/37719/3//COMMIT_MSG@12 PS3, Line 12:
Remove duplicate sign-off.
Done
https://review.coreboot.org/c/coreboot/+/37719/2/src/mainboard/biostar/am1ml... File src/mainboard/biostar/am1ml/bootblock.c:
https://review.coreboot.org/c/coreboot/+/37719/2/src/mainboard/biostar/am1ml... PS2, Line 85: /* Enable serial decode */
already done in hudson_lpc_decode()
Done
https://review.coreboot.org/c/coreboot/+/37719/2/src/mainboard/biostar/am1ml... PS2, Line 102: ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
duplicate of two lines above
You lost ite_kill_watchdog() now completely?
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37719
to look at the new patch set (#5).
Change subject: biostar/am1ml: Switch away from ROMCC_BOOTBLOCK ......................................................................
biostar/am1ml: Switch away from ROMCC_BOOTBLOCK
Change-Id: I7a972b531183b08af7b325bd686cf3eb7558082f Signed-off-by: Sergej Ivanov getinaks@gmail.com --- M src/mainboard/biostar/am1ml/Kconfig M src/mainboard/biostar/am1ml/Makefile.inc A src/mainboard/biostar/am1ml/bootblock.c D src/mainboard/biostar/am1ml/romstage.c 4 files changed, 91 insertions(+), 140 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/37719/5
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37719 )
Change subject: biostar/am1ml: Switch away from ROMCC_BOOTBLOCK ......................................................................
Patch Set 5: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/37719/2/src/mainboard/biostar/am1ml... File src/mainboard/biostar/am1ml/bootblock.c:
https://review.coreboot.org/c/coreboot/+/37719/2/src/mainboard/biostar/am1ml... PS2, Line 102: ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
You lost ite_kill_watchdog() now completely?
Done
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37719 )
Change subject: biostar/am1ml: Switch away from ROMCC_BOOTBLOCK ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37719/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/37719/5//COMMIT_MSG@8 PS5, Line 8: 1. Tested how? Line with: TEST=… 2. Please elaborate, how the switch was done. Basically move everything from `romstage.c` to `bootblock.c`?
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37719 )
Change subject: biostar/am1ml: Switch away from ROMCC_BOOTBLOCK ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37719/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/37719/5//COMMIT_MSG@8 PS5, Line 8:
- Tested how? Line with: TEST=… […]
I am not going to request or wait for this.
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37719 )
Change subject: biostar/am1ml: Switch away from ROMCC_BOOTBLOCK ......................................................................
Patch Set 5:
Needs manual rebase on current master.
Hello Kyösti Mälkki, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37719
to look at the new patch set (#6).
Change subject: biostar/am1ml: Switch away from ROMCC_BOOTBLOCK ......................................................................
biostar/am1ml: Switch away from ROMCC_BOOTBLOCK
Switching was done by moving a SIO configuration and a clocks setup from 'romstage.c' to 'bootblock.c'
TEST=Boots into Ubuntu Linux 16.04.6 without a problem.
Change-Id: I7a972b531183b08af7b325bd686cf3eb7558082f Signed-off-by: Sergej Ivanov getinaks@gmail.com --- M src/mainboard/biostar/am1ml/Kconfig M src/mainboard/biostar/am1ml/Makefile.inc A src/mainboard/biostar/am1ml/bootblock.c D src/mainboard/biostar/am1ml/romstage.c 4 files changed, 91 insertions(+), 140 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/37719/6
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37719 )
Change subject: biostar/am1ml: Switch away from ROMCC_BOOTBLOCK ......................................................................
Patch Set 6: Code-Review+1
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37719 )
Change subject: biostar/am1ml: Switch away from ROMCC_BOOTBLOCK ......................................................................
Patch Set 6: -Code-Review
You need to pull current master and rebase on it before this can be merged.
Hello Kyösti Mälkki, Paul Menzel, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37719
to look at the new patch set (#7).
Change subject: biostar/am1ml: Switch away from ROMCC_BOOTBLOCK ......................................................................
biostar/am1ml: Switch away from ROMCC_BOOTBLOCK
Switching was done by moving a SIO configuration and a clocks setup from 'romstage.c' to 'bootblock.c'
TEST=Boots into Ubuntu Linux 16.04.6 without a problem.
Change-Id: I7a972b531183b08af7b325bd686cf3eb7558082f Signed-off-by: Sergej Ivanov getinaks@gmail.com --- M src/mainboard/biostar/Kconfig M src/mainboard/biostar/am1ml/Kconfig M src/mainboard/biostar/am1ml/Makefile.inc A src/mainboard/biostar/am1ml/bootblock.c D src/mainboard/biostar/am1ml/romstage.c 5 files changed, 91 insertions(+), 146 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/37719/7
Hello Kyösti Mälkki, Paul Menzel, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37719
to look at the new patch set (#8).
Change subject: biostar/am1ml: Switch away from ROMCC_BOOTBLOCK ......................................................................
biostar/am1ml: Switch away from ROMCC_BOOTBLOCK
Switching was done by moving a SIO configuration and a clocks setup from 'romstage.c' to 'bootblock.c'
TEST=Boots into Ubuntu Linux 16.04.6 without a problem.
Change-Id: I7a972b531183b08af7b325bd686cf3eb7558082f Signed-off-by: Sergej Ivanov getinaks@gmail.com --- M src/mainboard/biostar/Kconfig M src/mainboard/biostar/am1ml/Kconfig M src/mainboard/biostar/am1ml/Kconfig.name M src/mainboard/biostar/am1ml/Makefile.inc A src/mainboard/biostar/am1ml/bootblock.c D src/mainboard/biostar/am1ml/romstage.c 6 files changed, 93 insertions(+), 148 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/37719/8
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37719 )
Change subject: biostar/am1ml: Switch away from ROMCC_BOOTBLOCK ......................................................................
Patch Set 8: Code-Review+2
Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37719 )
Change subject: biostar/am1ml: Switch away from ROMCC_BOOTBLOCK ......................................................................
biostar/am1ml: Switch away from ROMCC_BOOTBLOCK
Switching was done by moving a SIO configuration and a clocks setup from 'romstage.c' to 'bootblock.c'
TEST=Boots into Ubuntu Linux 16.04.6 without a problem.
Change-Id: I7a972b531183b08af7b325bd686cf3eb7558082f Signed-off-by: Sergej Ivanov getinaks@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/37719 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/mainboard/biostar/Kconfig M src/mainboard/biostar/am1ml/Kconfig M src/mainboard/biostar/am1ml/Kconfig.name M src/mainboard/biostar/am1ml/Makefile.inc A src/mainboard/biostar/am1ml/bootblock.c D src/mainboard/biostar/am1ml/romstage.c 6 files changed, 93 insertions(+), 148 deletions(-)
Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved
diff --git a/src/mainboard/biostar/Kconfig b/src/mainboard/biostar/Kconfig index 6469d4e..43896a3 100644 --- a/src/mainboard/biostar/Kconfig +++ b/src/mainboard/biostar/Kconfig @@ -20,9 +20,6 @@
source "src/mainboard/biostar/*/Kconfig.name"
-config BIOSTAR_BOARDS_DISABLED - bool "Boards from vendor are disabled" - endchoice
source "src/mainboard/biostar/*/Kconfig" diff --git a/src/mainboard/biostar/am1ml/Kconfig b/src/mainboard/biostar/am1ml/Kconfig index 866fc66..9eaa6fb 100644 --- a/src/mainboard/biostar/am1ml/Kconfig +++ b/src/mainboard/biostar/am1ml/Kconfig @@ -14,15 +14,11 @@ # GNU General Public License for more details. #
-config BOARD_BIOSTAR_AM1ML - def_bool n - if BOARD_BIOSTAR_AM1ML
config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_4096 - #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY16_KB select FORCE_AM1_SOCKET_SUPPORT select GFXUMA diff --git a/src/mainboard/biostar/am1ml/Kconfig.name b/src/mainboard/biostar/am1ml/Kconfig.name index 0980c2e..da7a677 100644 --- a/src/mainboard/biostar/am1ml/Kconfig.name +++ b/src/mainboard/biostar/am1ml/Kconfig.name @@ -1,2 +1,2 @@ -#config BOARD_BIOSTAR_AM1ML -# bool"AM1ML" +config BOARD_BIOSTAR_AM1ML + bool"AM1ML" diff --git a/src/mainboard/biostar/am1ml/Makefile.inc b/src/mainboard/biostar/am1ml/Makefile.inc index f8895fa..4dde2cf 100644 --- a/src/mainboard/biostar/am1ml/Makefile.inc +++ b/src/mainboard/biostar/am1ml/Makefile.inc @@ -13,6 +13,8 @@ # GNU General Public License for more details. #
+bootblock-y += bootblock.c + romstage-y += buildOpts.c romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c diff --git a/src/mainboard/biostar/am1ml/bootblock.c b/src/mainboard/biostar/am1ml/bootblock.c new file mode 100644 index 0000000..f198fe6 --- /dev/null +++ b/src/mainboard/biostar/am1ml/bootblock.c @@ -0,0 +1,89 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <amdblocks/acpimmio.h> +#include <bootblock_common.h> +#include <device/pnp_ops.h> +#include <superio/ite/common/ite.h> +#include <superio/ite/it8728f/it8728f.h> + +#define SERIAL_DEV PNP_DEV(0x2e, IT8728F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8728F_GPIO) +#define ENVC_DEV PNP_DEV(0x2e, IT8728F_EC) + +static void ite_evc_conf(pnp_devfn_t dev) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_write_config(dev, 0xf1, 0x40); + pnp_write_config(dev, 0xf4, 0x80); + pnp_write_config(dev, 0xf5, 0x00); + pnp_write_config(dev, 0xf6, 0xf0); + pnp_write_config(dev, 0xf9, 0x48); + pnp_write_config(dev, 0xfa, 0x00); + pnp_write_config(dev, 0xfb, 0x00); + pnp_exit_conf_state(dev); +} + +static void ite_gpio_conf(pnp_devfn_t dev) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_write_config(dev, 0x25, 0x80); + pnp_write_config(dev, 0x26, 0x07); + pnp_write_config(dev, 0x28, 0x81); + pnp_write_config(dev, 0x2c, 0x06); + pnp_write_config(dev, 0x72, 0x00); + pnp_write_config(dev, 0x73, 0x00); + pnp_write_config(dev, 0xb3, 0x01); + pnp_write_config(dev, 0xb8, 0x00); + pnp_write_config(dev, 0xc0, 0x00); + pnp_write_config(dev, 0xc3, 0x00); + pnp_write_config(dev, 0xc8, 0x00); + pnp_write_config(dev, 0xc9, 0x07); + pnp_write_config(dev, 0xcb, 0x01); + pnp_write_config(dev, 0xf0, 0x10); + pnp_write_config(dev, 0xf4, 0x27); + pnp_write_config(dev, 0xf8, 0x20); + pnp_write_config(dev, 0xf9, 0x01); + pnp_exit_conf_state(dev); +} + +void bootblock_mainboard_early_init(void) +{ + volatile u32 *addr32; + u32 t32; + + /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */ + pm_write8(0xea, 0x1); + + /* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */ + addr32 = (u32 *)0xfed80e28; + t32 = *addr32; + t32 &= 0xfff8ffff; + *addr32 = t32; + + /* Enable Auxiliary Clock1, disable FCH 14 MHz OscClk */ + addr32 = (u32 *)0xfed80e40; + t32 = *addr32; + t32 &= 0xffffbffb; + *addr32 = t32; + + /* Configure SIO as made under vendor BIOS */ + ite_evc_conf(ENVC_DEV); + ite_gpio_conf(GPIO_DEV); + + /* Enable serial output on it8728f */ + ite_kill_watchdog(GPIO_DEV); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/biostar/am1ml/romstage.c b/src/mainboard/biostar/am1ml/romstage.c deleted file mode 100644 index 6c1581b..0000000 --- a/src/mainboard/biostar/am1ml/romstage.c +++ /dev/null @@ -1,139 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Sergej Ivanov getinaks@gmail.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <device/pnp_ops.h> -#include <device/pci_ops.h> -#include <console/console.h> -#include <northbridge/amd/agesa/state_machine.h> -#include <southbridge/amd/common/amd_defs.h> -#include <southbridge/amd/agesa/hudson/hudson.h> -#include <superio/ite/common/ite.h> -#include <superio/ite/it8728f/it8728f.h> - -#define SERIAL_DEV PNP_DEV(0x2e, IT8728F_SP1) -#define GPIO_DEV PNP_DEV(0x2e, IT8728F_GPIO) -#define ENVC_DEV PNP_DEV(0x2e, IT8728F_EC) - -#define MMIO_NON_POSTED_START 0xfed00000 -#define MMIO_NON_POSTED_END 0xfedfffff -#define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 + (x)) - -static void ite_evc_conf(pnp_devfn_t dev) -{ - pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_write_config(dev, 0xf1, 0x40); - pnp_write_config(dev, 0xf4, 0x80); - pnp_write_config(dev, 0xf5, 0x00); - pnp_write_config(dev, 0xf6, 0xf0); - pnp_write_config(dev, 0xf9, 0x48); - pnp_write_config(dev, 0xfa, 0x00); - pnp_write_config(dev, 0xfb, 0x00); - pnp_exit_conf_state(dev); -} - -static void ite_gpio_conf(pnp_devfn_t dev) -{ - pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_write_config(dev, 0x25, 0x80); - pnp_write_config(dev, 0x26, 0x07); - pnp_write_config(dev, 0x28, 0x81); - pnp_write_config(dev, 0x2c, 0x06); - pnp_write_config(dev, 0x72, 0x00); - pnp_write_config(dev, 0x73, 0x00); - pnp_write_config(dev, 0xb3, 0x01); - pnp_write_config(dev, 0xb8, 0x00); - pnp_write_config(dev, 0xc0, 0x00); - pnp_write_config(dev, 0xc3, 0x00); - pnp_write_config(dev, 0xc8, 0x00); - pnp_write_config(dev, 0xc9, 0x07); - pnp_write_config(dev, 0xcb, 0x01); - pnp_write_config(dev, 0xf0, 0x10); - pnp_write_config(dev, 0xf4, 0x27); - pnp_write_config(dev, 0xf8, 0x20); - pnp_write_config(dev, 0xf9, 0x01); - pnp_exit_conf_state(dev); -} - -void board_BeforeAgesa(struct sysinfo *cb) -{ - u32 val, t32; - u8 byte; - pci_devfn_t dev; - u32 *addr32; - - /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for - * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA - * even though the register is not documented in the Kabini BKDG. - * Otherwise the serial output is bad code. - */ - outb(0xD2, 0xcd6); - outb(0x00, 0xcd7); - - /* Set LPC decode enables. */ - pci_devfn_t dev2 = PCI_DEV(0, 0x14, 3); - pci_write_config32(dev2, 0x44, 0xff03ffd5); - - /* Enable the AcpiMmio space */ - outb(0x24, 0xcd6); - outb(0x1, 0xcd7); - - /* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */ - addr32 = (u32 *)0xfed80e28; - t32 = *addr32; - t32 &= 0xfff8ffff; - *addr32 = t32; - - /* Enable Auxiliary Clock1, disable FCH 14 MHz OscClk */ - addr32 = (u32 *)0xfed80e40; - t32 = *addr32; - t32 &= 0xffffbffb; - *addr32 = t32; - - /* enable SIO LPC decode */ - dev = PCI_DEV(0, 0x14, 3); - byte = pci_read_config8(dev, 0x48); - byte |= 3; /* 2e, 2f */ - pci_write_config8(dev, 0x48, byte); - - /* enable serial decode */ - byte = pci_read_config8(dev, 0x44); - byte |= (1 << 6); /* 0x3f8 */ - pci_write_config8(dev, 0x44, byte); - - /* This functions configure SIO as it been done under vendor bios */ - printk(BIOS_DEBUG, "ITE CONFIG ENVC\n"); - ite_evc_conf(ENVC_DEV); - printk(BIOS_DEBUG, "ITE CONFIG GPIO\n"); - ite_gpio_conf(GPIO_DEV); - printk(BIOS_DEBUG, "ITE CONFIG DONE\n"); - - - ite_kill_watchdog(GPIO_DEV); - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ - int i; - for (i = 0; i < 200000; i++) - val = inb(0xcd6); - - outb(0xEA, 0xCD6); - outb(0x1, 0xcd7); - - post_code(0x50); -}
-
Kyösti Mälkki (Code Review) -
Paul Menzel (Code Review)
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Sergej Ivanov (Code Review)