Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82236?usp=email )
Change subject: mb/google/brox: Sending End of Post (EOP) asynchronously ......................................................................
mb/google/brox: Sending End of Post (EOP) asynchronously
Currently EOP message is sent to CSE late in the boot flow. Instead send it asynchronously to save ~10 ms in boot time.
BUG=b:337330958 TEST=Build Brox BIOS Image and boot to OS.
Change-Id: I229d16a5dcd072958db3f59a9c364bf7508b3047 Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com --- M src/mainboard/google/brox/Kconfig M src/soc/intel/alderlake/Kconfig 2 files changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/82236/1
diff --git a/src/mainboard/google/brox/Kconfig b/src/mainboard/google/brox/Kconfig index 940f3a4..efe10d2 100644 --- a/src/mainboard/google/brox/Kconfig +++ b/src/mainboard/google/brox/Kconfig @@ -29,7 +29,7 @@ select MAINBOARD_HAS_TPM2 select PMC_IPC_ACPI_INTERFACE select SOC_INTEL_CSE_LITE_SKU -# select SOC_INTEL_CSE_SEND_EOP_ASYNC + select SOC_INTEL_CSE_SEND_EOP_ASYNC select SOC_INTEL_COMMON_BLOCK_USB4 select SOC_INTEL_COMMON_BLOCK_TCSS select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index b124b14..e0afe5a 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -82,7 +82,7 @@ select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_CLIENT select SOC_INTEL_COMMON_RESET - select SOC_INTEL_CSE_SEND_EOP_LATE if !BOARD_GOOGLE_BRYA_COMMON + select SOC_INTEL_CSE_SEND_EOP_LATE if !BOARD_GOOGLE_BRYA_COMMON && !BOARD_GOOGLE_BROX_COMMON select SOC_INTEL_CSE_SET_EOP select SOC_INTEL_GFX_MBUS_JOIN if MAINBOARD_HAS_CHROMEOS && BMP_LOGO select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
-
Karthik Ramasubramanian (Code Review)