[L] Change in coreboot[main]: soc/intel/skylake: Drop redundant PcieRpEnable

[Angel Pons (Code Review)]

Attention is currently required from: Erik van den Bogaert, Frans Hendriks, Jan Samek, Jeremy Soller, Jonathon Hall, Michael Niewöhner, Michał Żygowski, Nico Huber, Piotr Król, Reagan, Sean Rhodes, Tim Crawford.

Angel Pons has posted comments on this change by Nico Huber. ( https://review.coreboot.org/c/coreboot/+/79917?usp=email )

Change subject: soc/intel/skylake: Drop redundant PcieRpEnable
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Patch Set 2:

(1 comment)

File src/mainboard/razer/blade_stealth_kbl/devicetree.cb:

https://review.coreboot.org/c/coreboot/+/79917/comment/754b4df6_279602f1?usp... :
PS2, Line 190: 		device ref pcie_rp1	on  end
> IIRC, it's because a PCI device has to have a function 0 so it can be enumerated.

Yes.
> If the root port corresponding to function 0 isn't enabled, the PCH promotes the first enabled function to function 0.

It's actually software-configurable, and I think you can swap any set of functions. However, FSP does this configuration on newer Intel platforms. On older Intel platforms, coreboot configures this and (depending on the platform) can even set up function numbers so that they're contiguous ("coalesce" them); see `RPFN` register in southbridge code as well as `pcie_port_coalesce` devicetree setting.