[S] Change in coreboot[master]: soc/amd/*/acpi: add comment about p_lvl[2,3]_lat FADT field usage

[Felix Held (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held.

Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/73231

to look at the new patch set (#3).

Change subject: soc/amd/*/acpi: add comment about p_lvl[2,3]_lat FADT field usage
......................................................................

soc/amd/*/acpi: add comment about p_lvl[2,3]_lat FADT field usage

The latency values in the _CST package override the values in the
p_lvl2_lat and p_lvl3_lat FADT fields. In Picasso, Cezanne, Mendocino,
Phoenix and Glinda generate_cpu_entries generates the _CST packages for
each CPU device. The coreboot code for Stoneyridge doesn't generate _CST
packages for the CPU objects, but those are provided via the PSTATE SSDT
binaryPI generates and agesa_write_acpi_tables gets and adds to the ACPI
tables. The AGESA reference code also sets those two FADT entries to the
equivalents of ACPI_FADT_C2_NOT_SUPPORTED and ACPI_FADT_C3_NOT_SUPPORTED
so this also matches the AGESA behavior.

From the ACPI 6.4 spec: "Values provided by the _CST object override
P_LVLx values in P_BLK and P_LVLx_LAT values in the FADT."

TEST=C-State latency reported by Linux doesn't change on Mandolin
(Picasso) or Careena (Stoneyridge).

Signed-off-by: Felix Held 
Change-Id: I1116a3013576b18b6f521604d6b0a9d75b971e0b
---
M src/soc/amd/cezanne/acpi.c
M src/soc/amd/glinda/acpi.c
M src/soc/amd/mendocino/acpi.c
M src/soc/amd/phoenix/acpi.c
M src/soc/amd/picasso/acpi.c
M src/soc/amd/stoneyridge/acpi.c
6 files changed, 38 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/73231/3