Rasheed Hsueh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46293 )
Change subject: mb/google/volteer: add generic DDR4 SPDs for Lindar ......................................................................
mb/google/volteer: add generic DDR4 SPDs for Lindar
Add Makefile.inc to include six generic DDR4 SPDs for the following parts for Lindar:
DRAM Part Name DRAM ID to assign MT53E512M32D2NP-046 WT:E 0 (0000) K4U6E3S4AA-MGCR 1 (0001) H9HCNNNBKMMLXR-NEE 2 (0010) MT53E512M32D2NP-046 WT:E 8 (1000) K4U6E3S4AA-MGCR 9 (1001) H9HCNNNBKMMLXR-NEE 10 (1010)
BUG=b:161089195 TEST="FW_NAME=Lindar emerge-volteer coreboot" and verify it builds without error.
Signed-off-by: rasheed.hsueh rasheed.hsueh@lcfc.corp-partner.google.com Change-Id: I088517090da0565e55ffa978cb90cb879f3b6702 --- M src/mainboard/google/volteer/variants/lindar/memory/Makefile.inc M src/mainboard/google/volteer/variants/lindar/memory/dram_id.generated.txt M src/mainboard/google/volteer/variants/lindar/memory/mem_list_variant.txt 3 files changed, 15 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/46293/1
diff --git a/src/mainboard/google/volteer/variants/lindar/memory/Makefile.inc b/src/mainboard/google/volteer/variants/lindar/memory/Makefile.inc index 8c96e06..8f17e14 100644 --- a/src/mainboard/google/volteer/variants/lindar/memory/Makefile.inc +++ b/src/mainboard/google/volteer/variants/lindar/memory/Makefile.inc @@ -2,4 +2,9 @@ ## This is an auto-generated file. Do not edit!!
SPD_SOURCES = -SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = K4U6E3S4AA-MGCL +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E +SPD_SOURCES += lp4x-spd-1.hex # ID = 1(0b0001) Parts = K4U6E3S4AA-MGCR +SPD_SOURCES += lp4x-spd-1.hex # ID = 2(0b0010) Parts = H9HCNNNBKMMLXR-NEE +SPD_SOURCES += lp4x-spd-1.hex # ID = 8(0b1000) Parts = MT53E512M32D2NP-046 WT:E +SPD_SOURCES += lp4x-spd-1.hex # ID = 9(0b1001) Parts = K4U6E3S4AA-MGCR +SPD_SOURCES += lp4x-spd-1.hex # ID = 10(0b1010) Parts = H9HCNNNBKMMLXR-NEE diff --git a/src/mainboard/google/volteer/variants/lindar/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/lindar/memory/dram_id.generated.txt index 9bf0bd9..9ed10ec 100644 --- a/src/mainboard/google/volteer/variants/lindar/memory/dram_id.generated.txt +++ b/src/mainboard/google/volteer/variants/lindar/memory/dram_id.generated.txt @@ -1,2 +1,7 @@ DRAM Part Name ID to assign -K4U6E3S4AA-MGCL 0 (0000) +MT53E512M32D2NP-046 WT:E 0 (0000) +K4U6E3S4AA-MGCR 1 (0001) +H9HCNNNBKMMLXR-NEE 2 (0010) +MT53E512M32D2NP-046 WT:E 8 (1000) +K4U6E3S4AA-MGCR 9 (1001) +H9HCNNNBKMMLXR-NEE 10 (1010) diff --git a/src/mainboard/google/volteer/variants/lindar/memory/mem_list_variant.txt b/src/mainboard/google/volteer/variants/lindar/memory/mem_list_variant.txt index a226d2f..47159f8 100644 --- a/src/mainboard/google/volteer/variants/lindar/memory/mem_list_variant.txt +++ b/src/mainboard/google/volteer/variants/lindar/memory/mem_list_variant.txt @@ -1 +1,3 @@ -K4U6E3S4AA-MGCL +MT53E512M32D2NP-046 WT:E +K4U6E3S4AA-MGCR +H9HCNNNBKMMLXR-NEE
Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46293 )
Change subject: mb/google/volteer: add generic DDR4 SPDs for Lindar ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46293/1/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/lindar/memory/dram_id.generated.txt:
https://review.coreboot.org/c/coreboot/+/46293/1/src/mainboard/google/voltee... PS1, Line 2: MT53E512M32D2NP-046 WT:E 0 (0000) : K4U6E3S4AA-MGCR 1 (0001) : H9HCNNNBKMMLXR-NEE 2 (0010) : MT53E512M32D2NP-046 WT:E 8 (1000) : K4U6E3S4AA-MGCR 9 (1001) : H9HCNNNBKMMLXR-NEE 10 (1010) Hi Furquan, there are 3 memory in the mem_list_variant.txt however there are 5 generated setting here (MT53E512M32D2NP-046 WT:E and K4U6E3S4AA-MGCR are duplicated), is this expected?
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46293 )
Change subject: mb/google/volteer: add generic DDR4 SPDs for Lindar ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46293/1/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/lindar/memory/dram_id.generated.txt:
https://review.coreboot.org/c/coreboot/+/46293/1/src/mainboard/google/voltee... PS1, Line 2: MT53E512M32D2NP-046 WT:E 0 (0000) : K4U6E3S4AA-MGCR 1 (0001) : H9HCNNNBKMMLXR-NEE 2 (0010) : MT53E512M32D2NP-046 WT:E 8 (1000) : K4U6E3S4AA-MGCR 9 (1001) : H9HCNNNBKMMLXR-NEE 10 (1010)
Hi Furquan, there are 3 memory in the mem_list_variant. […]
No this is not correct. It looks like this and Makefile.inc were manually created?
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46293 )
Change subject: mb/google/volteer: add generic DDR4 SPDs for Lindar ......................................................................
Patch Set 1: Code-Review-1
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46293 )
Change subject: mb/google/volteer: add generic DDR4 SPDs for Lindar ......................................................................
Patch Set 1: Code-Review-1
This should use generic SPDs and consolidate DRAM IDs. Please see comment here : https://buganizer.corp.google.com/issues/170264065#comment9
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46293 )
Change subject: mb/google/volteer: add generic DDR4 SPDs for Lindar ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/46293/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46293/1//COMMIT_MSG@7 PS1, Line 7: DDR4 LPDDR4x
https://review.coreboot.org/c/coreboot/+/46293/1//COMMIT_MSG@9 PS1, Line 9: DDR4 LPDDR4x
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46293 )
Change subject: mb/google/volteer: add generic DDR4 SPDs for Lindar ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46293/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46293/1//COMMIT_MSG@13 PS1, Line 13: MT53E512M32D2NP-046 WT:E 0 (0000) : K4U6E3S4AA-MGCR 1 (0001) : H9HCNNNBKMMLXR-NEE 2 (0010) : MT53E512M32D2NP-046 WT:E 8 (1000) : K4U6E3S4AA-MGCR 9 (1001) : H9HCNNNBKMMLXR-NEE 10 (1010) Please align the DRAM IDs.
Rasheed Hsueh has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/46293 )
Change subject: mb/google/volteer: add generic DDR4 SPDs for Lindar ......................................................................
Abandoned
LCFC will modify the memory strap of the schematic/BOM in the proto phase.
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Furquan Shaikh (Code Review) -
Nick Vaccaro (Code Review)
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Paul Menzel (Code Review)
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Rasheed Hsueh (Code Review)
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Zhuohao Lee (Code Review)